Abstract: A method in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes for servicing a first memory access request by a first node of the computer network pertaining to a memory block having a home node different from the first node in the computer network. The computer network has no natural ordering mechanism and natural broadcast for servicing memory access requests from the plurality of nodes. The home node has no centralized directory for tracking states of the memory block in the plurality of nodes. The method includes the step of receiving via the common network infrastructure at the home node from the first node the first memory access request for the memory block.

Abstract: A processor architecture containing multiple closely coupled processors in a form of symmetric multiprocessing system is provided. The special coupling mechanism allows it to speculatively execute multiple threads in parallel very efficiently. Generally, the operating system is responsible for scheduling various threads of execution among the available processors in a multiprocessor system. One problem with parallel multithreading is that the overhead involved in scheduling the threads for execution by the operating system is such that shorter segments of code cannot efficiently take advantage of parallel multithreading. Consequently, potential performance gains from parallel multithreading are not attainable. Additional circuitry is included in a form of symmetrical multiprocessing system which enables the scheduling and speculative execution of multiple threads on multiple processors without the involvement and inherent overhead of the operating system.

Abstract: A technique to detect and correct single bit errors and to detect paired bit errors in a data block. Two bits of the data block are paired and transferred on the same data path in different cycles. Check bits are computed prior to transferring the data block. A syndrome bits vector is computed when the data block is received. The syndrome bits vector includes a number of syndrome bits that is identical to the number of check bits. A value of the syndrome bits vector is used to detect and correct single bit errors and to detect paired double bit errors that occur in the data block without using an extended check bit. If the syndrome bits vector contains all zero bits, the data block is accepted without modification. If the syndrome bits vector is identical to a predetermined special vector V, a paired double bit error has occurred and either an unrecoverable error message is generated or a re-operation on the data block is requested.

Abstract: A system and method for storing error correction check words in computer memory modules. Check bits stored in physically adjacent locations within a dynamic random access memory (DRAM) chip are assigned to different check words. By assigning check bits to check words in this manner, multi-bit soft errors resulting from errors in two or more check bits stored in physically adjacent memory locations will appear as single-bit errors to an error correction subsystem. Similarly, the likelihood of multi-bit errors occurring in the same check word may be reduced.

Abstract: A method and apparatus for thermally isolating a temperature sensor mounted on a printed circuit board from a heat generating component mounted on the printed circuit board is provided. Generally, a thermal isolation region, which may be comprised of a plurality of openings in the printed circuit board, is disposed about the temperature sensor to interrupt conductive transfer of heat from the heat generating component to the temperature sensor. The openings extend sufficiently far into the printed circuit board to remove at least a portion of a conductive layer, such as a power plane from the region surrounding the temperature sensor. Electrical power and signals may be provided to the temperature sensor through regions intermediate the openings.

Abstract: A system and method for providing hot swap capability with minimal changes in a system which uses existing circuitry and drivers. In one embodiment, a computer system has a host processor and a hot-swap-capable device, each coupled to a Compact PCI bus. The device includes one or more pre-existing circuits (ASICs and/or standard off-the-shelf circuits) and corresponding pre-existing drivers. A hot-swap-capable bus bridge is interposed between the circuits and the Compact PCI bus to provide hot swap functionality while allowing the pre-existing circuits and drivers to be used without modification. In one embodiment, an Intel 21554 is used as the hot-swap-capable bus bridge. The 21554 is programmed to emulate a transparent bridge. Modified drivers in the OBP firmware and OS software allow the system to recognize the 21554 in this transparent configuration and to probe the secondary side of the 21554 for the circuits.

Abstract: A system and method for determining the desired decoupling capacitors for power distribution systems having frequency dependent target impedance. In one embodiment, the target impedance may be a function of frequency, and thus may vary in value over a frequency range from 0 Hz to a corner frequency. A specific quantity of decoupling capacitors may be selected to provide decoupling for the power distribution for a given frequency within the frequency range. A total impedance provided by the specific quantity of selected decoupling capacitors may be calculated and compared to the calculated target impedance for the given frequency. If the total impedance provided by the specific quantity of selected decoupling capacitors is greater than the target impedance for the given frequency, the impedance may be adjusted by changing the quantity of capacitors. Capacitors may continue to be added until the total impedance is less than the target impedance.

Abstract: A method and apparatus for combined transaction reordering and buffer management. The apparatus may include a buffer, a first generator circuit and a second generator circuit. The buffer is configured to store memory transaction responses received from a memory controller in a plurality of addressable locations. The first generator circuit is configured to generate a first memory transaction request encoded with a first tag corresponding to an address in the buffer in response to receiving a first memory request. The second generator circuit is configured to generate a second tag using the size of said first memory request added to the first tag. The first generator circuit may be further configured to generate a second memory transaction request encoded with the second tag corresponding to a second address in the buffer in response to receiving a second memory request successive to the first memory request.

Abstract: A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while preventing a faulty board from causing a system crash. The system includes a centerplane that mounts multiple expander boards. Each expander board in turn connects a microprocessor board and an I/O board to the centerplane. Prior to testing, the replacement I/O board becomes a part of a dynamic system domain software partition after it has been inserted into an expander board of the multiprocessing computer system. Testing an I/O board involves executing a process using a microprocessor and memory on a microprocessor board to perform hardware tests on the I/O board. An error cage, address transaction cage, and interrupt transaction cage isolate any errors generated while the I/O board is being tested.

Abstract: A method and mechanism for arbitrating access to a bus. A client which is parked on a bus is allowed to gain access to the bus without having to go through arbitration. A client which is parked on the bus does not request access to the bus before beginning a transaction. If another client makes a high priority request for the bus, it gains access to the bus over a parked client. The parked client keeps a count of detected high priority request cycles. Upon reaching a threshold, the parked client requests the bus. The high priority client may then be made aware of the parked client's need for the bus and yield at an appropriate time.

Abstract: A system and method for isolating the execution of a plurality of applications. The applications may utilize or share one or more “original” classes. Only one copy of each original class is maintained, regardless of how many applications utilize it. Static fields are extracted from the original classes. A separate copy of the static fields is created for each of the utilizing applications. A static field class which includes instance fields corresponding to the static fields may be created, wherein each instance of the static field class corresponds to one of the utilizing applications. Access methods for the one or more static fields may be created, wherein the access methods are operable to access the corresponding separate copy of the static fields based upon the identity of the utilizing application.

Abstract: A system and method providing address broadcast synchronization using multiple switches. The system for concurrently providing addresses to a plurality of devices includes a first switch and a second switch. The first switch is coupled to receive address requests from a first plurality of sources. The first switch is configured to output the address request from the first plurality of sources. The second switch is coupled to receive address requests from a second plurality of sources. The second switch is configured to receive the address request from the first plurality of sources from the first switch. The second switch is further configured to delay the address request from the second plurality of sources prior to arbitrating between ones of the address request from the second plurality of sources and ones of the address request from the first party of sources received from the first switch.

Abstract: A system and method for analyzing simultaneous switching noise. In one embodiment, a model may be provided for the electronic circuit to be analyzed. The electronic circuit may be an integrated circuit, a multi-chip module, a printed circuit assembly, or other type, and may in some embodiments include combinations of these types. The electronic circuit may include a plurality of drivers, each of which may be coupled to a power plane, a ground plane, and a transmission line. The connection of the driver may be accurately modeled in this manner. Each driver may be configured to switch between a logic high voltage and a logic low voltage. The modeled electronic circuit may also include a voltage source coupled to the power plane and the ground plane, a voltage regulator module, and a plurality of decoupling capacitors. The simultaneous switching of a plurality of drivers, from a logic high to a logic low, or vice versa, may be simulated.

Abstract: A network file system and method wherein a storage area network Universal File System allows any host in a heterogeneous based storage area network to read or write data as if in its native format. Any host coupled to the storage area network may be configured to access any storage device on the storage area network. By augmenting the operating system of a host, the host is enabled to mount the Universal File System. Subsequent to mounting the Universal File System, a host may read data from and write data to the Universal File System.

Abstract: A method and system for improving memory access in Accelerated Graphics Port systems. The method and system associate a transaction id with individual data transactions within a number of Accelerated Graphics Port (AGP) pipelined data transactions, and identify the individual data transactions within the number of AGP pipelined data transactions via the transaction id. In one instance, the association of a transaction id with individual data transactions includes but is not limited to associating a transaction id with each individual memory read request within a number of AGP pipelined memory read requests and associating an identical transaction id with each individual data unit, within a number of pipelined data units, corresponding to each individual memory read request within the number of AGP pipelined memory requests.

Abstract: A system and method for isolating the execution of a plurality of applications. A plurality of monitors are provided for a plurality of applications to access a static synchronized method. The applications are enabled to call the static synchronized method concurrently by accessing the static synchronized method through the plurality of monitors. A plurality of threads within one of the applications are excluded from calling the static synchronized method concurrently. The source code or bytecode for the synchronized method may be transformed by removing a method-level monitor and adding the plurality of monitors inside the method. In one embodiment, each static synchronized method is replaced with a corresponding static non-synchronized method. The applications may be further isolated by placing the static fields of shared classes into a static field class, which has one instance per utilizing application.

Abstract: An execution unit is provided for executing a first instruction which includes an opcode field, a first operand field, and a second operand field. The execution unit includes a first input register for receiving a first operand specified by a value of the first operand field, and a second input register for receiving a second operand specified by a value of the second operand field. The execution unit further includes a comparator unit which is coupled to receive a value of the opcode field for the first instruction. The comparator unit is also coupled to receive the first and second operand values from the first and second input registers, respectively. The execution further includes a multiplexer which receives a plurality of inputs. These inputs include a first constant value, a second constant value, and the values of the first and second operand.

Abstract: A computer-implemented directory access mechanism provides a directory service operable to access a network directory under a predetermined protocol by responding to an access request under the protocol for information available in a predetermined environment external to the directory. The directory service then uses the access method for the environment to access the information available in the environment. In this manner, data in the given environment can be accessed by a directory service operable under the given protocol by configuring an attribute access method and using this method to retrieve the information. The protocol can be the Lightweight Directory Access Protocol. The information to be accessed could typically be an attribute of an entry in the directory. An access control list (for example the Directory Access Control Domain) can contain not only control access rights for directory objects, but also the access methods for attributes of the directory objects.

Abstract: A system and method for monitoring a distributed fault tolerant computer system. A hardware counter mechanism (e.g. a countdown counter) is reset repeatedly by a software reset mechanism during normal operation, thereby preventing the counter mechanism from reaching a count indicative of the existence of a fault. A unit provides a signal to a bus indicative of the status (ON or OFF) of the unit. A management subsystem defines a configuration for the distributed fault tolerant computer system. The management subsystem is responsive to status signals on the bus and selectively reconfigures a stored representation in response to changing status signals on the bus.