Abstract: A component cage for detachable mounting an ancillary component such as a hard disc drive in a housing for an electronic circuit is described. The cage has internal step surfaces to engage support runners of the component. The formation of elongated slots in the cage to accommodate support runners is avoided, improving the electromagnetic shielding ability of the cage.

Abstract: An enclosure includes a base having an interior portion defined by a first side panel and a second side panel and a frame joined to the first side panel and the second side panel such that the frame extends across the interior portion the base. A computer system includes a motherboard having a central processing unit, a power supply capable of supplying power to the motherboard, and an enclosure capable of housing the motherboard and the power supply. The enclosure includes a base having an interior portion defined by a first side panel and a second side panel and a frame joined to the first side panel and the second side panel such that the frame extends across the interior portion of the base.

Abstract: Method and system for configuring a network computer to distinguish between a first address path for a first logging module and a second address path for a second logging module for a log report, using full distinguished names (FDNs) that provide first and second address paths for the first and second logging modules, where the first and second address paths have different object level addresses at an object level immediately below the root level. Where a local distinguished name (LDN) (or relative distinguished name RDN) is used for an address path, the system forwards a log report to an associated Log Server only if the first component of the address path is a selected object level address, such as ‘/system’.

Abstract: A system for capturing the data necessary for synthesizing an instruction stream for a microprocessor. An embodiment uses a microprocessor that is adapted to write its branch trace data to the main memory. This branch trace data includes whether the microprocessor took each conditional jump encountered during the execution of a program as well as the target location of each indirect jump. The preferred embodiment further includes a logic analyzer coupled to the primary expansion bus of the target computer system. The logic analyzer captures input/output reads and writes as well as DMA transactions to the main memory. Finally, a synthesis control card controls starting a data capture as well as facilitating the transfer of information from buffers in the main memory to the control computer system.

Abstract: A high-performance memory module. The memory module is designed for a computer system with a wide data path. The memory module is implemented using a small printed circuit board (PCB), with a plurality of memory chips and a connector mounted upon the PCB. Signal traces for control, address, and data signals are arranged in such a manner as to minimize the length of each signal trace, thereby saving PCB area. On the connector, an electrical ground pin is located between each pair of signal pins, which may allow for a low-resistance return current path, and may therefore allow the module to operate at higher clock frequencies. Furthermore, locating a ground pin between each pair of signal pins may help reduce signal interference, or “crosstalk”, thereby improving signal integrity of the memory module.

Abstract: A mechanism for exception and interrupt handling in multithreaded multiprocessors is provided. The mechanism allows the handling of exceptions and interruptions in a multithreaded multiprocessor computer, while hiding the multiprocessor nature of the computer from the operating system. Generally, when an operating system is cognizant of the multiprocessor nature of a computer, additional overhead may be required when handling exceptions and interruptions. Due to the overhead involved in saving and restoring processing states, the performance of a processor may be significantly impacted. Additional circuitry is provided which allows the multiprocessor nature of the computer to be hidden from the operating system, while minimizing the overhead necessary for proper handling.

Abstract: The present invention provides a method and apparatus for replacing a filter. The apparatus includes a receptacle adapted to receive a filter that is capable of filtering a first area. The apparatus further includes at least one supporting member to support at least a portion of the filter and at least a portion of a replacement filter, wherein both the filter and replacement filter are adapted to filter at least a portion of the first area for a selected duration.

Abstract: Several different systems and methods are described involving arbitration between asynchronous and isochronous data for access to a data transport resource (e.g., a bus or a memory controller). A first embodiment of a system (e.g., a computer system or a communication system) includes an arbiter coupled to the data transport resource, an asynchronous queue for storing asynchronous data, and an isochronous queue for storing isochronous data. The isochronous queue has a data level range divided into multiple portions. A number of memory locations within the isochronous queue may define the data level range of the isochronous queue. The arbiter arbitrates between the asynchronous queue and the isochronous queue for access to the data transport resource dependent upon the portion of the data level range in which a level of data resides within the isochronous queue. The level of data within the isochronous queue may be a number of memory locations between a write pointer and a read pointer.

Abstract: A method and apparatus for controlling output impedance of an input/output (I/O) circuit. In one embodiment, an I/O circuit includes a first plurality of resistive elements connected in parallel and a second plurality of resistive elements connected in parallel. Each of the resistive elements includes a control terminal. The control terminal may be used to activate or deactivate the resistive element. The control terminal for each resistive element may be controlled by a control circuit, which may be configured to activate one or more of the resistive elements. Each of the resistive elements of the first plurality may be of substantially different resistances, as may be true with the second plurality of resistive elements. Due to the substantially different resistances of each of the first and second pluralities of resistive elements, the resistive step sizes for the I/O circuit remain substantially equal as additional resistive elements are activated.

Abstract: The health of a process is monitored in a computer system by a process monitor. The monitored process (a configuration management system daemon (CMSD)) is not a child of the process monitor. The process monitor uniquely determines the identity of a monitored process and verifies the correct operation of the monitored process. In the absence of verification of the correct operation of the monitored process, the monitored process is caused to initiate. On successful initiation of the monitored process, the monitored process is uniquely identified to the system and is detached from the process monitor. Each monitored process is arranged to write, on initiation, its unique process identification information (PID) to a file, which file is then accessed by the process monitor to identify the process monitor. The process monitor can interrogate the operating system to verify correct operation of the CMSD.

Abstract: An integrated circuit is presented having a plurality of logic modules dispersed about a surface of a semiconductor substrate. Each logic module includes a set of control and status registers including at least one control register storing a control value. A functional unit of each logic module performs one or more logic functions dependent upon the control value stored in the control register. A central controller is coupled to the each of the logic modules. The central controller is adapted to receive address, data, and control signals (e.g., from signal lines of an external bus coupled to I/O pads of the integrated circuit), and issues read/write commands to read/write the control and status registers dependent upon the address, data, and control signals. A write command may, for example, modify the control value stored in a selected one of the control registers. The integrated circuit may include a bus which couples the central controller to each of the logic modules.

Abstract: A system and method for efficient layout of a display table. Given a description of a table, such as a markup language description, the table description may be parsed and data structures representing the table description may be created. The table description data structures may then be “inspected”, in order to determine the possible size of the table. Once the table has been inspected, the table may then be “apportioned”, based on the results of the inspection step. That is, final dimensions may be assigned to the table. The table coordinates may then be “normalized”, which may involve converting relative table coordinates into absolute coordinates. Table layout optimizations are described, e.g., in order to efficiently handle various aspects of table layout, such as table cells that span multiple columns or rows, table cells that include nested tables, etc.

Abstract: A computer system is described including a processor for executing instructions, a memory module for storing instructions and data, and a memory controller coupled between the processor and the memory module. The memory controller provides a differential clock signal and memory access signals which are routed to the memory module. The memory module includes multiple memory devices coupled to a clock buffer. The clock buffer produces a new single-ended “regenerated” clock signal from the differential clock signal. The clock buffer includes an input buffer circuit and a phase-locked loop (PLL). The input buffer circuit receives the differential clock signal from the memory controller and produces a single-ended reference clock signal from the differential clock signal. The PLL produces the regenerated clock signal substantially at the same frequency of, and in synchronization with, the single-ended reference clock signal produced by the input buffer circuit.

Abstract: In one embodiment of the present invention, a carrier plate assembly for use in an electrical system is disclosed, comprising a carrier plate capable of securing at least one system board. Each system board is capable of being inserted and removed from the carrier plate assembly without disturbing another system board connected to the carrier plate assembly. The carrier plate assembly is capable of releasable attachment to the electronic system and is capable of being inserted and removed from the electronic system without disturbing another assembly connected to the electronic system.

Abstract: A method for datum sharing between modular computer system components, includes determining a position and orientation of a motherboard, defining at least one datum feature in a primary chassis describing the position and orientation of the motherboard, and defining at least one datum feature in a secondary chassis corresponding to the at least one datum feature in the primary chassis. An apparatus for datum sharing includes at least one datum feature of the primary chassis, at least one datum feature of the motherboard, wherein a location of the at least one datum feature of the primary chassis is based upon the at least one datum feature of the motherboard, and at least one datum feature of the secondary chassis, wherein a location of the at least one datum feature of the secondary chassis is based upon the location of the at least one datum feature of the primary chassis.

Abstract: Various systems and methods for reducing the power consumption of CSRs (Control and Status Registers) within an integrated circuit (IC) are disclosed. In one embodiment, an IC includes a plurality of CSRs. Each CSR includes one or more flip-flops that are used to store one or more bits of control and/or status information for an associated device on the IC. The IC also includes one or more clock gates. Each clock gate is coupled to provide a gated clock signal to one or more of the flip-flops in a respective one of the CSRs. Each clock gate is configured to output a clock signal as the gated clock signal if a clock enable signal that corresponds to the respective CSR is asserted. The IC also includes one or more clock gating units that are each configured to generate the clock enable signal for a respective one of the CSRs.

Abstract: The present invention provides a method and apparatus for packaging high frequency electrical and/or electro-optical components. The present invention provides a package which may be surface mounted on a board with other electrical components. The shielding provided by the package minimizes electromagnetic interference with other electrical components on the board. The package includes a controlled impedance I/O interface for coupling with the electrical and/or electro-optical component(s) in the package. The package interface may also include a differential I/O capability to further control electromagnetic fields generated at the interface. Additionally, the package may include an optical link provided by one or more optical fibers extending from the package.

Abstract: A system and method for maintaining storage object consistency across a distributed storage network including a migratable repository of last resort which stores a last or only remaining data replica that may not be deleted. The method includes the steps of monitoring data requests to the repository of last resort, deciding whether to move the repository of last resort, and migrating the repository of last resort.

Abstract: A circuit comprises an active filter with linear elements and a tuning circuit with linear elements of the same type as the filter circuit. A backward counter generates a count value that represents a time constant of the tuning circuit. The initial value of the backward counter contains information concerning the relationship between the time constant of the filter circuit and the tuning circuit. A decoder creates a digital code responsive to the count value which is used to switch an array of linear elements in order to tune the time constant of the filter to approximately a desired design value.

Abstract: The present invention discloses methods and apparatus for installing printed circuit boards within an electronic assembly. One embodiment of the present invention is an electro-magnetic interference shielding apparatus for an electronic assembly comprising a shielding partition that separates a first compartment from a second compartment. The apparatus further comprises a top enclosure capable of engaging with the shielding partition to form a plurality of contact seams. The contact seams are capable of restricting electro-magnetic interference from passing through the shielding apparatus. The top enclosure can be capable of tool-free installation and removal to provide access to the interior of the electronic assembly.