Abstract: A method for determining the bypass capacitors in order to achieve a target impedance over a wide frequency range. In one embodiment, a power distribution system of an electronic circuit includes at least one pair of planar conductors, including a power plane and a ground plane. A first capacitor bank may be defined to provide bypassing in a frequency range extending from a maximum frequency down to a first frequency (also referred to as a deviation frequency). The electrical characteristics, or parameters of the first capacitor bank may include a first capacitance, a first resistance, and a first inductance (C10, R10, and L10, respectively). The first resistance may be set to be less than or equal to the required target impedance for the frequency range covered by the first capacitor bank.

Abstract: A method and system for serializing a transient object-oriented database into a persistent form. The persistent form is a grammatical form, an expression of an object-oriented database in a textual form according to a grammar. The grammatical form is human-readable and human-editable. The grammar is designed to be platform-independent and programming-language-independent and therefore descriptive of any hierarchical object-oriented database. An object-oriented database is expressed as a plurality of entries in a transient, hierarchical, object-oriented form. The tree of entries is navigated and each entry is written to the persistent form as text according to the grammar. The serialized form stores only the key state of the database, not a “snapshot” of memory. Therefore, the persistent, serialized form is smaller than the in-memory, transient form of the object-oriented database.

Abstract: A data address prediction structure for a superscalar microprocessor is provided. The data address prediction structure predicts a data address that a group of instructions is going to access while that group of instructions is being fetched from the instruction cache. The data bytes associated with the predicted address are placed in a relatively small, fast buffer. The decode stages of instruction processing pipelines in the microprocessor access the buffer with addresses generated from the instructions, and if the associated data bytes are found in the buffer they are conveyed to the reservation station associated with the requesting decode stage. Therefore, the implicit memory read associated with an instruction is performed prior to the instruction arriving in a functional unit. The functional unit is occupied by the instruction for a fewer number of clock cycles, since it need not perform the implicit memory operation.

Abstract: A data visualization arrangement for facilitating the display of data items comprising a selected region of an object in a selected one of a plurality of display modes. The arrangement comprises a data object store, an interface, an object region retrieval component and a display. The data object store stores the data object, the data object comprising a plurality of data items in a predetermined organization. The interface receives a region identification for identifying a particular region of the object and a display mode identification. The object region retrieval component retrieves data items from a region of the data object as identified by the region identification received by the interface. Finally, the display receives the data items as retrieved by the object region retrieval mechanism and displays them in the display mode as identified by the display mode identification.

Abstract: A memory access request handling unit is arranged between a source of memory access requests and a data storage element that is the target of the memory access requests. The memory access request handling unit comprises a queue made up of a number of queue elements, each being capable of temporarily storing one memory access request. Comparison logic is arranged to monitor a window of the queue and to select one or more of the queue elements, representing memory access requests not yet transmitted to the data storage element, for transmission to the data storage element. The selection is made on the basis of a comparison between the memory access requests held in the queue and one or both of a priority value set for each memory access request and a list of memory access requests that are currently pending at the data storage element, the list being maintained in a list store of the memory access request handling unit.

Abstract: A communication arrangement facilitates transfer of messages among a plurality of processes in with a computer, the computer having a memory shared by the processes. The communication arrangement comprises, allocated to each process, a plurality of buffers, and a plurality of postboxes each associated with one of the other processes. Each process includes a message size determination module and a message transfer module. The message size determination module is configured to determine whether a message to be transferred to another process can be accommodated by a postbox.

Abstract: A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgment for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.

Abstract: A method and system for compiling a grammatical form of an object-oriented database into an intermediate form of that database. The grammatical form is a persistent form of an object-oriented database expressed in a human-readable and human-editable textual form according to a grammar. The textual form is parsed into a series of tokens. The tokens are compiled into a plurality of entries. The plurality of entries are expressed in an intermediate form. The intermediate form comprises an array of intelligent entry objects which encapsulate data with methods for manipulating that data. The methods include creating a database entry, creating a property associated with an entry, creating an attribute associated with an entry or property, querying the last entry, property, or attribute created, and finalizing entry storage. The intermediate form lacks the infrastructure of the database, but the intermediate form can be used to populate the object-oriented database with entries.

Abstract: A system and method for memory allocation from a heap comprising memory blocks of a uniform fixed size. Each memory block has a status bit. A binary status key stores a Boolean value indicating free memory. The heap is scanned in order until a sequence of a requested quantity of free contiguous memory blocks is found or NULL is returned. Each scanned free memory block is marked un-free by assigning its status bit to the logical negative of the binary status key. If the end of the heap is reached before a sequence of sufficient quantity is found, all reachable blocks are marked as free. The binary status key is flipped such that all memory blocks which were marked free are now un-free, and vice versa. Any memory block whose corresponding structure has become unreferenced is reclaimed for future use. The scan then continues from the beginning of the heap. In another embodiment, a memory allocation for a partitioned data structure from a heap of fixed-size memory blocks may be used.

Abstract: A computer implemented method and a computer program product includes a first computer readable code construct configured to handle request messages. This comprises receiving a request message and having an associated user name which is associated with a remote user on a network. Further, making an access determination to determine whether the forwarding of the request message is authorized, and finally when forwarding of the request message is authorized, the message to a target system is forwarded.

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. It also comprises a bridge control mechanism configured to be operable, in an operational mode to permit access by at least one of the first and second processing sets to bridge resources and to the device bus and, in an error mode, to prevent access by the processing sets to the device bus and to permit restricted access to at least one of the processing sets to at least predetermined bridge resources. By providing restricted access to selected parameters held in the bridge during an error mode, the bridge can act as a secure repository for information which can be used by the processing sets to investigate the error and hopefully to recover therefrom, while preventing I/O devices connected to device bus from being corrupted by a faulty processing set. Storage in the bridge provides for buffering data pending resolution of the error.

Abstract: A recovery logging method wherein when a node in a computer network becomes unavailable, file systems which require verification and are locked are logged in a recovery log and checking of other file systems continues. In this manner, the host node effectively utilizes time which would otherwise be spent waiting for a file system to become available. Upon completing available file system verifications, those file systems which were logged are checked for availability via background processing. When a logged file system becomes available, it is then verified. During the time spent waiting for a logged file system to become available, the affected node is available for other processing.

Abstract: An apparatus is disclosed for capturing and transferring internal system activity of a computer under test. In one embodiment, the apparatus includes a bus interface, a memory, an external interface, and circuitry coupling the three together. The bus interface connects to an internal system bus of the system under test. The memory is for storing information indicative of internal system activity. The external interface couples to an external, monitoring system. The circuitry partitions the memory into at least two banks, each having multiple buffers. One of the multiple buffers in each bank is a trace buffer that receives instruction trace information from the processor of the system under test. The multiple buffers may further include a system memory image buffer, a processor data buffer, and a bus activity buffer. When any one of the buffers in a given bank of the memory becomes full, a bank switch occurs.

Abstract: A system and method for initializing deterministic source-synchronous transfers between devices in a computer system using one or more ratio bits to indicate a ratio between clocks. In an exemplary computer system, one or more processors are each coupled to a bridge. The one or more ratio bits are used to indicate a ratio between the system clock of a first device, such as a processor, and the system clock of a second device, such as the bridge. Each device may also operate at a multiple of its system clock. Once the one or more ratio bits have been stored, the first device can determine when edges of its operating clock correspond to edges of the operating clock of the second device. The use of the one or more ratio bits may advantageously allow devices in the computer system to operate on different system clocks without dedicated signal lines or pins to indicate the frequencies of those different system clocks.

Abstract: A method is provided, the method comprising associating each net of traces in a list of nets of the traces on a routed PCB with a parallelism index value and sorting the list of the nets of the traces on the routed PCB based on the parallelism index values. The method also comprises providing a list of victim nets of traces on the routed PCB based on the parallelism index values, each of the victim nets on the list of the victim nets associated with at least one offending net of traces on the routed PCB.

Abstract: A method and apparatus for switching between threads of a program in response to a long-latency event. In one embodiment, the long-latency events are load or store operations which trigger a thread switch if there is a miss in the level 2 cache. In addition to providing separate groups of registers for multiple threads, a group of program address registers pointing to different threads are provided. A switching mechanism switches between the program address registers in response to the long-latency events.

Abstract: A probabilistic queue lock divides requesters for a lock into at least three sets. In one embodiment, the requesters are divided into the owner of the lock, the first waiting contender, and the other waiting contenders. The first waiting contender is made probabilistically more likely to obtain the lock by having it spin faster than the other waiting contenders. Because the other waiting contenders spin more slowly, the first waiting contender is more likely to be able to observe the free lock and acquire it before the other waiting contenders notice that it is free. The first of the other waiting contenders that determines that the previous first waiting contender has acquired the lock is promoted to be the new first waiting contender and begins spinning fast. Because only the first waiting contender is spinning fast on the lock, it is probable that only the first waiting contender will attempt to acquire the lock when it becomes available.

Abstract: An asymmetric multi-converter power supply including a first converter and a second converter coupled to provide power to an output node. A control circuit is coupled to the second converter and is configured to selectively enable the second converter depending upon a voltage at the output node. The control circuit may be configured to enable the second converter only in response to determining that the voltage at the output node is not within a predetermined range. Alternatively, the first converter is configured to provide power through a first series inductor and the second converter is configured to provide power to the output node through a second series inductor. The second series inductor having a smaller inductance than the first series inductor. Additionally, the second converter may be characterized by a transient response time that is faster than a transient response time of the first converter.

Abstract: A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to restrict the global transfer of local transactions, a plurality of address partitions are defined: global space, local space, remote read space, and remote read and write space. Process private and local data is accessed using local space. Global data is accessed using global space. In one embodiment, a kernel of the operating system is resident in the local space of each node. Because the memory space where the kernel resides is designated as local space, no other nodes can write to, or corrupt, the node's kernel.

Abstract: An integrated circuit package comprising EMI containment features. The EMI containment features include a first EMI containment configuration and a second EMI containment configuration. The second EMI containment configuration is disposed around the first EMI containment configuration. The first and second EMI containment configurations include vias coupled to at least one ground plane of the integrated circuit package.