Abstract: A comparator comprises a switching means for supplying two different threshold voltages to the comparator upon a first and a second control signal, respectively. The second control signal is enabled by a rising or a falling edge of the comparator output that is coupled to a control means providing the second control signal. The time interval that a varying input signal requires to change its amplitude crossing and in between the two threshold voltages can thus be detected by two subsequent rising or falling edges of the comparator output without the adverse influence of the comparator's meta-stability.

Abstract: A cache memory includes a plurality of memory chips, or other separately addressable memory sections, which are configured to collectively store a plurality of cache lines. Each cache line includes data and an associated cache tag. The cache tag may include an address tag which identifies the line as well as state information indicating the coherency state for the line. Each cache line is stored across the memory chips in a row formed by corresponding entries (i.e., entries accessed using the same index address). The plurality of cache lines is grouped into separate subsets based on index addresses, thereby forming several separate classes of cache lines. The cache tags associated with cache lines of different classes are stored in different memory chips. During operation, the cache controller may receive multiple snoop requests corresponding to, for example, transactions initiated by various processors.

Abstract: A data storage system includes a computer coupled to a non-volatile storage, such as a disk drive. The computer includes a block cache for storing cached copies of data blocks, and a hash table that stores hash values corresponding to the data blocks. Prior to writing back a modified cache block to the non-volatile storage, a log recorder of the computer stores an updated hash value corresponding to the modified cache block within a write-ahead hash log, which is also contained in non-volatile storage. The log recorder creates a log record including an updated hash value and an address corresponding to a modified cache block. The log recorder additionally maintains a first pointer value indicative of log records that have been stored to the write-ahead hash log, and a second pointer value indicative of the most recent log record stored in the write-ahead hash log for which a corresponding modified cache block has been stored to the non-volatile storage.

Abstract: A method of synchronizing the generation and consumption of isochronous data in a computer system. In one embodiment, a computer system implements a method comprising providing a plurality of clocks to a plurality of isochronous sinks or sources configured to generate or consume the isochronous data, outputting a master clock signal to the plurality of isochronous sinks or sources, synchronizing said clocks to said master clock signal so that the generation or consumption of the isochronous data is synchronized to said master clock signal, outputting said master clock signal to an interrupt controller, and generating an interrupt based on said master clock signal, wherein a processor schedules one or more tasks that generate or consume data based on said interrupt. The isochronous sinks or sources may also be synched to a multiple of the master clock signal.

Abstract: A digital communication system is presented implementing a data transmission method which allows each of a pair of communication devices coupled to a transmission line to both transmit and receive data during each cycle of a clock signal (i.e., simultaneous bidirectional data transmission). The digital communication system includes a first and second communication devices coupled to opposite ends of a transmission line. Both the first and second communication devices operate in response to a periodic clock signal. The first and second communication devices simultaneously: (i) drive an output data signal upon the transmission line during a first portion of a period of the clock signal, and (ii) receive an input signal from the transmission line during a remainder of the period of the clock signal. The communication devices may be coupled to receive the clock signal via a clock signal line, or may include circuitry to generate and synchronize two separate clock signals.

Abstract: A circuit and method for stopping a clock tree while maintaining PLL lock. A clock circuit includes a locked loop circuit and a clock tree distribution network. The locked loop circuit receives an input clock signal and generates a PLL output clock depending upon a feedback signal. The clock tree is coupled to the locked loop circuit and conveys the PLL output clock to a plurality of clocked circuit elements. The clock circuit further includes a gating circuit and a feedback delay circuit. The gating circuit is coupled between the locked loop circuit the clock tree distribution network and selectively inhibits the PLL output clock from clocking the clock tree distribution network. The feedback delay circuit provides the feedback signal, which represents a delayed version of the PLL output clock, during operation including when the gating circuit inhibits the PLL output clock from clocking the clock tree.

Abstract: A technique for arbitrating and selecting one access request to a shared memory from among multiple contenders is disclosed. In a first aspect, the invention includes a method for accessing a shared memory. The method includes receiving a plurality of access requests; presenting a plurality of characteristics for each access request; ascertaining a plurality of operational characteristics; and selecting one of the access requests for processing upon consideration of the access request characteristics and the operational characteristics. In a second aspect, the invention includes an arbitration and select logic (“ASL”) unit. The ASL unit comprises a plurality of input sorting units, each input sorting unit capable of receiving a respective access request and a merge and interleave unit (“MIU”).

Abstract: A software fault tolerant computer system includes a primary virtual machine and a secondary virtual machine. The secondary virtual machine is operable to replicate the primary virtual machine by replicating operations performed on the primary virtual machine. The primary and the secondary virtual machines are further operable to test for equivalent operation of the primary and secondary virtual machines at predetermined stages of operation. This provides software fault tolerance wherein both a unit of replication and a component that implements the fault tolerance mechanisms is a virtual machine (VM). Since a VM as used by the invention has full knowledge of the semantics of application-level code, fault tolerance mechanisms can be provided by the VMs without requiring any increase in application complexity. Co-ordination of replicated states and computations is achieved with characteristics of both active and passive replication.

Abstract: A digital data processing apparatus configured to selectively transfer data between a primary data storage element and an associated data file on a secondary data storage element. The apparatus includes a primary data storage element that stores data for access by one or more processes, as well as a non-volatile secondary data storage element. A directory stores attributes reflecting a state of one or more subsets of data in respective sets. During transfer of data between the primary data storage element and the secondary data storage element, the apparatus stores data corresponding to the attribute in a second file on the second storage element, in response to detecting the transfer and detecting the attribute indicates an atomic state corresponding to the first data.

Abstract: An enclosure for an electronics assembly, comprises (i) a housing (1) having a recess (36); and (ii) a module (40) for holding one or more components of the assembly, the module being insertable into the recess by sliding, and removable therefrom by sliding in a direction opposite to the direction of insertion; and (iii) a spring retaining element (48) located in one of the housing and the module, the element being in the form of a resiliently deformable arm that engages the other of the housing and the module when the module is inserted into position within the recess in order to prevent removal of the module from the recess. The arm can be manually bent to release the module from the recess, but the housing or the module allows a degree of movement of the retaining element during release of the module that is insufficient to allow the arm to bend beyond its elastic limit. The enclosure enables the module to be held firmly in place, but allows quick and easy release for maintenance of the assembly.

Abstract: Apparatus is disclosed for viewing computer generated images and for tracking the positions of the user's head and hand. One alternative of the apparatus includes a frame element, versatilely mountable, with sensors for the head tracking of a user whose bodily movement is constrained to a small area. Short range and inexpensive sensors are deployed for tracking the position of the user's head; these sensors are deployed partly on a on the user's head and partly on the tracking frame. All the electronics for tracking and user input are enclosed in a mobile pack. In another alternative of the tracking invention natural forces such as gravity, the Earth's magnetic field, and inertia are used, so additional references. The display allows for interchangeable optical elements so that it may be tailored to suit the needs of a particular user or application.

Abstract: An electronics assembly comprises: (i) a frame (1); and (ii) a motherboard (16) that is removable from the frame. One or more motherboards (20) extend in a plane generally perpendicular to the plane of the motherboard; and a number of elongate guides (24) are provided for the daughterboards to enable each daughterboard to be moved toward the motherboard into engagement therewith and away from the motherboard out of engagement therefrom. The motherboard (16) has at least one location element (32) thereon, which can engage one of the elongate guides (24) in order to locate the guides and the motherboard with respect to one another. This assembly enables accurate positioning of the daughterboards and the motherboard for forming electrical connections between them even where large tolerances are present in other parts of the assembly.

Abstract: An electronics assembly comprises: (i) a frame (1); (ii) a motherboard (16) that is located within the frame; and (iii) one or more daughterboards (20) that extend in a plane generally perpendicular to the plane of the motherboard. The motherboard has a protective shield (40, 52) that extends over the major surface of the motherboard that is oriented toward the or each daughterboard. The shield has one or more apertures (54) therein to allow electrical connection between the motherboard and the or each daughterboard.

Abstract: An optical interconnect is provided that optically connects two adjacent printed circuit boards, or electrical component. The optical interconnect includes a floating frame which is flexibly connected to one electrical component. The floating frame includes a plurality of optical guides. The optical guides are connected to the electrical component either electronically or optically. A second frame, coupled to a second electrical component also contains a plurality of optical guides. A mechanical guide assembly positions the first frame and the second frame are optically coupled. The optical guide in the second frame connects to the second electrical component providing a path for a signal from the first electrical component to the second electrical component.

Abstract: A method and apparatus for locating integrated circuit defects associated with different aspects of the integrated circuit industry. The integrated circuit is configured in a known failing mode, with a first power supply providing a constant voltage and variable current. Next, one or more additional dedicated power supplies are connected to various points of interest throughout the integrated circuit, wherein these dedicated power supplies have a preset current and the voltage is allowed to vary. The integrated circuit is then scanned with a laser beam, which induces current changes on in the integrated circuit especially in defective areas. These current changes then cause voltage changes on the dedicated power supplies. When such a voltage change occurs on the dedicated power supplies, its position is noted.

Abstract: An apparatus and method for distributing multiple clock signals to multiple devices using an encoded clock signal is provided. A source clock signal can be encoded to result in an encoded system clock. The encoded system clock can be distributed to multiple devices in a computer system. The devices can decode the encoded system clock signal to generate a system clock signal and a global clock signal. The system clock signal and the global clock signal can then be distributed to their respective clock loads on each device. In certain embodiments, additional information, such as state information, can be encoded into the encoded system clock. A device can be configured to decode the additional information and can alter its state accordingly.

Abstract: A method and system for providing an intelligent intermediate form of an object-oriented database. The intermediate form is derived from a grammatical form of an object-oriented database through the process of compilation. The grammatical form is a persistent form of an object-oriented database expressed in a human-readable and human-editable textual form according to a grammar. The intermediate form comprises an array of intelligent entry objects which encapsulate data with methods for manipulating that data. The methods include creating a database entry, creating a property associated with an entry, creating an attribute associated with an entry or property, querying the last entry, property, or attribute created, and finalizing entry storage. The intermediate form lacks the infrastructure of the database, but the intermediate form can be used to populate the object-oriented database with entries.

Abstract: A method of direct plane attachment of capacitors is disclosed. In one embodiment, a printed circuit board (PCB) having a signal layer, a first conductive plane, and a second conductive plane is provided. The signal layer may be the outermost layer of the PCB, while the first conductive layer may be arranged between the signal layer and the second conductive layer. A cavity may be formed in the printed circuit board, wherein the cavity extends from the signal layer down to the first conductive plane. The cavity may be large enough to accommodate one or more capacitors. A first terminal of the capacitor may be attached to the first conductive plane. The second terminal of the capacitor may be mounted within an opening in the first conductive plane. The method may allow a bypass capacitor to be directly coupled to a power or reference plane.

Abstract: A method and system for customizing the transformation of an object-oriented database to and from a grammatical form. A grammatical form is an expression of an object-oriented database in a textual form according to a grammar. The transformation customizer is a plug-in which provides translation of primitive data types to and from complex data types for compilation and serialization processes. A complex data type is defined in terms of one or more primitive data types. One or more values in the object-oriented database are expressed in terms of the complex data type. During serialization, the plug-in module is invoked. The plug-in understands both the complex data type and the primitive data types. The values from the object-oriented database are translated from the complex data type to the primitive data types. For customizing compilation, one or more values expressed in terms of the primitive data types are translated to the complex data type when the plug-in is invoked.

Abstract: A method is provided for operating an electronic device by monitoring operating characteristics of the electronic device, and determining from the monitored operating characteristics to operate at least a portion of components within the electronic device in a first, second, or third mode of operation. The first, second, and third modes of operation consume power at first, second, and third different rates. At least a portion of the components are instructed to switch between the first, second, and third modes.