Abstract: An apparatus for containing electromagnetic interference (EMI). The apparatus includes an enclosure for an EMI producing component. The enclosure has a set of springable tabs extending from a top edge of the enclosure and a set of pins extending from a bottom edge of the enclosure. The pins are placed through a grounding ring and a printed circuit board to align and ground the enclosure. The tabs contact a heatsink disposed over the enclosure.

Abstract: An electronics assembly may include a frame (1) and a motherboard module (18) have cooperating temporary supporting elements (50, 54, 60, 62) that can be engaged to support one edge of the motherboard module until some of the securing elements have been engaged to secure the motherboard module to the frame or after the securing elements have been released. The provision of temporary supporting elements enables a service engineer to support the motherboard module with a single hand while securing it in position with the other hand.

Abstract: A memory expansion module with stacked memory packages. A memory module is implemented using stacked memory packages. Each of the stacked memory packages contains multiple memory chips, typically DRAMs (dynamic random access memory). The memory may be organized into multiple banks, wherein a given memory chip within a stacked memory package is part of one bank, while another memory chip in the same package is part of another bank. The memory module also includes a clock driver chip and a storage unit. The storage unit is configured to store module identification information, such as a serial number. The storage unit is also configured to store information correlating electrical contact pads on the module with individual signal pins on the stacked memory packages. This may allow an error to be quickly traced to a specific pin on a stacked memory package when an error is detected on the memory bus by an error correction subsystem.

Abstract: A system that enables a memory controller to control data transfers with memory modules, such as DIMMs (double in-line memory modules), of either a “by 4” (×4) type or a non-by-4 type (non-×4). Both ×4 and non-×4 DIMMs may be used in the system simultaneously, and the memory controller dynamically adjusts its enable and other signals as needed. Data strobe signals are provided to and from DIMMs over a data strobe transfer circuits which in the case of a non-×4 DIMM handles data strobes for an entire byte of data, while in the case of ×4 DIMM the data transfer circuit handles data strobes for one nibble (four bits) of a byte of data. A hybrid data mask/data strobe transfer circuit handles the other nibble of a byte of data in the case of data transfers for ×4 DIMMs, and handles data mask signals for write operations for non-×4 DIMMs.

Abstract: An electronics assembly comprises a frame (1) that contains a motherboard (8) and a plurality of daughterboards (10). The frame has an opening opposite the motherboard to allow insertion of the daughterboards into the frame or removal of the daughterboards from the frame. The frame also has an injector/ejector mechanism (16, 18) for each daughterboard that is located on the daughterboard or the frame and a flange (28) that extends adjacent to the opening and on which the injector/ejector mechanism of each daughterboard is attached or engages at different locations along the length thereof. The flange (28) is divided into separate sections (30) that correspond to the different locations to allow the flange to flex at any adjacent location during insertion of a daughterboard without the flexing affecting the position of any adjacent location of the flange with respect to the motherboard.

Abstract: A system and method for detecting parity errors in a system where clients are configured to arbitrate amongst themselves for a grant to a central resource is provided. A client may send a request for access to the central resource to all other clients. In the event that multiple clients request access to the central resource substantially simultaneously, the clients may each determine which client should be granted the right to send its request to the central resource. The clients may make this determination according to an arbitration scheme. Where multiple requests occur substantially simultaneously, each client may calculate a parity based on the number of requests it receives. The clients may each convey their parity to the central resource. The clients may convey these parities to the central resource at about the same time as the granted request is conveyed to the central resource by its respective client.

Abstract: A system and method for implementing a multi-level interrupt scheme in a computer system is provided. Bus devices and a bus controller may be coupled to a shared bus in a computer system. The bus may include an interrupt line for each bus device coupled to the bus. A bus device may be configured to convey an interrupt using its designated interrupt line. Each bus device may be configured to convey different types of interrupt signals on its interrupt line depending on an interrupt priority level of a given interrupt. The bus controller may be configured to receive interrupt signals from each bus device coupled to the bus and may arbitrate amongst the interrupt signals based on the interrupt priority level of each interrupt signal. The bus controller may grant the interrupt that corresponds to the highest priority level. If multiple interrupts correspond to the same highest priority level in a group of interrupts, then the bus controller may use any suitable arbitration scheme to grant an interrupt.

Abstract: A virtual channel buffer bypass in a computer system input/output node. A control unit of an input/output node for a computer system includes a buffer circuit configured to receive control commands. The buffer circuit may include a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected control commands that belong to the respective virtual channel. The buffer circuit may also be configured to determine whether each of the plurality of buffers is empty prior to storing a particular control command corresponding to a given one of the plurality of buffers. In addition, the buffer circuit may be configured to cause the particular control command to bypass the given one of the plurality of buffers in response to determining that each of the plurality of buffers is empty.

Abstract: A system and method providing address broadcast synchronization using multiple switches. The system for concurrently providing addresses to a plurality of devices includes a first switch and a second switch. The first switch is coupled to receive address requests from a first plurality of sources. The first switch is configured to output the address request from the first plurality of sources. The second switch is coupled to receive address requests from a second plurality of sources. The second switch is configured to receive the address request from the first plurality of sources from the first switch. The second switch is further configured to delay the address request from the second plurality of sources prior to arbitrating between ones of the address request from the second plurality of sources and ones of the address request from the first party of sources received from the first switch.

Abstract: An electronics assembly, for example a computer, comprises an enclosure, and a heat-generating component located within the enclosure. A duct extends from the region of an aperture in a wall of the enclosure to the component and a fan is located within the duct to cause a flow of air from outside the enclosure directly to the heat-generating component.

Abstract: Apparatus and methods for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the planar conductors. The methods include bypass capacitor selection criteria and electrical resistance determination criteria based upon simulation results. An exemplary electrical power distribution structure produced by one of the methods includes a pair of parallel planar conductors separated by a dielectric layer, n discrete electrical capacitors, and n electrical resistance elements, where n≧2. Each of the n discrete electrical resistance elements is coupled in series with a corresponding one of the n discrete electrical capacitors between the planar conductors. The n capacitors have substantially the same capacitance C, mounted resistance Rm, mounted inductance Lm, and mounted resonant frequency fm-res.

Abstract: An efficient method is described for laying out a table for display. The method may be used to display tables on a small footprint device, such as a smart cellular phone, a personal data assistant, a handheld computer, etc. Small footprint devices typically have smaller displays than other computing systems such as desktop computers. In one embodiment the method is employed to lay out HTML tables in a web browser running on a small footprint device.

Abstract: A method and apparatus for passing device configuration information to a shared controller. In one embodiment, a host controller may be configured to read configuration from one or more peripheral devices coupled to a serial bus. The peripheral devices may include coder/decoder (codec) circuitry, and may be implemented using a riser card. The host controller may employ one or more of several different techniques in order to read configuration information from the peripheral device. The configuration information at a minimum includes a device identifier, which may identify the vendor and the function of the device. Additional information needed to configure the device to communicate over the peripheral bus may also be obtained with a read of the device, or various lookup mechanisms, such as a lookup table or a tree-like data structure.

Abstract: A test circuit for exposing higher order speed paths. A test circuit includes a clock generation circuit coupled to a test clock control unit. The clock generation circuit is configured to receive an input clock signal and to generate an output clock signal. The test clock control unit is configured to selectively provide a user programmable test vector or a fixed test vector to control the generation of the output clock signal by the clock generation circuit depending upon a state of a first mode select signal.

Abstract: A system and method for transferring a data stream between devices having different clock domains. The method initiates a serial data stream between a transmitter and a receiver. The transmitter operates according to a first clock having a first clock rate, and the receiver operates according to a second clock having a second clock rate. A ratio between the second clock rate and the first clock rate is an integer number greater than or equal to one. A first state is provided over a serial line between the transmitter and the receiver One or more start bits are provided over the serial line. The start bits indicate a second state different from the first state. One or more ratio bits are provided over the serial line after the start bit. The ratio bits indicate the ratio between the second clock rate and the first clock rate. The start bits are received. Using a transition between the first state and the second state evident in receiving each of the start bits, the ratio bits are received.

Abstract: A method for initializing a computing system comprising a plurality of devices which communicate on a communication link comprising a plurality of independent point-to-point links is provided, each of the point-to-point links interconnecting a respective pair of the plurality of devices. The method includes a link initialization procedure comprising initially configuring each respective pair of devices to communicate on the respective interconnecting link using common communication parameters, including a common frequency and a common link width. The link initialization procedure also may include an optimization procedure for determining maximum communication parameters for each interconnected pair of devices. If the maximum compatible parameters differ from the common parameters for any pair of devices, then the pair of devices may be reconfigured to communicate on the interconnecting link using the maximum compatible parameters.

Abstract: A method and apparatus for packet-switched flow control of transaction requests in uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller a piori know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate.

Abstract: A rack mountable system unit includes a housing having first and second sides. First and second elongate plastics slides are secured to respective sides of the system unit. Each plastic slide is dimensioned to slide within a rack mountable rail and is tapered at one end thereof to facilitate insertion into the rail. The tapered end of the slides facilitates insertion into the rails and the use of plastics facilitates sliding. The maximum height of the slide is dimensioned to slide within the rack mountable rail. To further facilitate the sliding of the system unit along the racking, the sides include narrower portions alternating with portions dimensioned to slide within the rack mountable rail. The slides each have a flange and a releasable fixing at a front end thereof for securing the system unit to rack mountable rails.

Abstract: The electronic device with a system for enhancing the cooling of components located therein is provided. The device includes a housing with a fan positioned adjacent the housing and adapted for producing airflow within the housing. The printed circuit board is mounted within the housing, and a heat-producing device is mounted on the printed circuit board. The heatsink is coupled to the heat-producing device, and a shroud is mounted on the printed circuit board and extends up to the heatsink so as to improve airflow in the region adjacent the heatsink.