Abstract: A method for preparing a germanium layer (22) adjacent to a germanium silicon layer (20). Initially, a P-germanium silicon layer (16) is deposited on to an N-germanium silicon layer (14). The continuous germanium layer (22) is formed by heating the layers (14 and 16) in a steam oxidation step to approximately 1000 degrees Centigrade to transform the P-germanium silicon layer (16) into the P-germanium layer (18) and a SiO.sub.2 layer (22). A method for forming a heterojunction bipolar transistor utilizing a P-germanium layer (50) is also disclosed.

Abstract: There is disclosed a circuit and method for providing bias voltage levels which are precisely controlled as a function of temperature. The circuit is arranged to mix a precise bandgap regulated voltage with a temperature compensated circuit to provide the required output. The temperature compensated circuit is in turn arranged to mimic the temperature sensitive components in the output circuit. A reduced voltage level is created which introduces no temperature related voltage changes.

Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.

Abstract: A FIFO 12 has a status flag generator 14. The status flag generator 14 includes a register programmable to "N". It also includes two sets of gray-code counters and a register (22,23,21;26,25,24) that are driven by separate READ and WRITE CLKS. The registers and counters are connected to comparators (31-36) for generating a plurality of signals that are input to output latches (41-43). The status flag generator is capable of generating status signals of FULL, HALF-FULL, EMPTY, FULL-N and EMPTY+N. N is a user-defined number that is programmed into a register 20 that is selectively connected to one or more of the programmable gray-code counters (23,24).

Abstract: A method and structure for protecting an integrated circuit from electrostatic discharges are disclosed. A Shockley diode (22) is connected to an input bond pad (12) and to a MOSFET transistor (17) which is desired to be protected. The normally high breakdown voltage required to drive the Shockley diode (22) into conduction is reduced by providing a trigger transistor (24) for prematurely triggering the diode (22). When the base-collector junction of the common emitter configured trigger transistor (24) is driven into avalanche breakdown by the electrostatic discharge, charged carriers (60) are generated, and attracted by the Shockley diode (22). The base (54) of the trigger transistor (24) is biased during normal operations iwth a supply voltage, and during electrostatic discharges to a higher voltage by an inherent Zener diode (64).

Abstract: A carrier-susceptor for use in a continuous chemical vapor deposition reactor system serves as a carrier, cover and heat susceptor for a semiconductor wafer being processes through the reactor system.

Abstract: An active pull down circuit for a logic circuit, having a true and a complement output, a pull down transistor coupled to one of the true and complement outputs, a bias element for biasing the pull down transistor on, and a charge coupling element coupled between the other of the true and complement outputs and a base of the pull down transistor for coupling charge from the other output to the pull down transistor to turn on the latter harder when the other output goes low.

Abstract: An apparatus and method for translating voltages between logic levels is provided having an input section (11), a level shifter section (89) and an output section (137). Input section (11) provides two control voltages to the level shifter section (89) in response to an input signal provided at input terminal (12). Level shifter section (89) comprises two inverters coupled to the control voltages. One inverter comprises p channel field-effect transistor (90) and n channel field-effect transistor (98). Another inverter comprises p channel field-effect transistor (106) and n channel field-effect transistor (114). For each inverter, the channel of the p channel field-effect transistor is over twice as wide as the channel of the n channel field-effect transistors. Each transistor (90, 98, 106 and 114) conducts current in response to a control voltage being anywhere within the voltage range, such that outputs of the inverters transition quickly in reponse to a transition of the control voltages.

Abstract: An integrated circuit (10) which includes primary circuit (12) and secondary circuit (17). An enabling circuit (16) allows package pins (15) to be shared between the primary circuit (12) and secondary circuit (17) responsive to voltages on the package pins (15). Enabling circuit (16) further includes disabling circuitry to disable the secondary circuit (17) responsive to a predetermined voltage on the V.sub.cc pin and enables the secondary circuit (17) responsive to a ground voltage on the V.sub.cc pin.

Abstract: The disclosure relates to a circuit and method of reducing inductive voltage spikes caused by an abrupt change in current by an output transistor, by providing an input node for receiving an input voltage signal, providing an output node, providing a first transistor coupled to the output node, receiving a predetermined voltage at the input node, controlling voltage control circuitry coupled between the input node and the first transistor and responsive to the predetermined voltage at the input node to control the voltage driving the first transistor with respect to time to provide a constant rate of change of current with respect to time in the first transistor and providing a second transistor coupled to the output node in parallel with the first transistor which turns on prior to the first transistor.

Abstract: Hysteresis effects in low frequency field effect transistor circuits are minimized by using biasing or clamping circuits including field effect transistors.

Abstract: An isolation structure for bipolar and CMOS circuits formed during the same processing steps to optimize the integration of bipolar and CMOS circuits. A deep trench (46) is formed in a semiconductor circuit for providing deep isolation for bipolar circuits. A shallow recess (56) is then formed simultaneous with a stepped sidewall structure of the deep trench. The recess (56) and the trench (46) are covered by an insulating oxide (60). and thereafter filled with an undoped polysilicon (62) to form the different isolating structures for the different types of circuits.

Abstract: Disclosed is a bipolar transistor and a method of fabrication thereof compatible with MOSFET devices. A transistor intrinsic base region (54) is formed in the face of a semiconductor well (22), and covered with a gate oxide (44). The gate oxide (44) is opened, and doped polysilicon is deposited thereover to form a polyemitter structure (68) in contact with the base region (54). Sidewall oxide (82, 84) is formed on the polyemitter strucure (60). A collector region (90) and an extrinsic base region (100) are formed in the semicondcutor well (22) and self aligned with respect to opposing side edges of the polyemitter sidewall oxide (82, 84).

Abstract: Disclosed is a device power supply in a semiconductor test system for supplying programmed test pattern voltages to a semiconductor device under test and for current range switching of current range resistors without effecting the output voltage of the device power supply.

Abstract: A method and film/interconnect lead combination for attaching a plurality of sets of interconnect leads on a strip of film using an adhesive which loses bonding strength upon being exposed to energy such as heat or ultra violet light. The film holds the interconnect leads firmly in their proper position for bonding to an integrated circuit chip and to a leadframe or substrate such as a printed wiring board or a ceramic substrate for hybrid circuits. Either during or after bonding the interconnect leads to the leadframe or substrate, energy is applied to the adhesive holding the interconnect leads to the film and the film is detached from the interconnect leads in a manner which will not damage the leads due to the reduced adhesive strength. Thus, the leadframe package will not enclose the film.

Abstract: A bipolar transistor formed in a trench depression such that a single impurity diffusing step is effective to form a buried collector layer electrically connected to a vertical collector conductor. The lateral diffusion forming the vertical collector conductor is effective to form the conductor with a uniform vertical doping profile, thereby reducing non-uniform series collector resistance characteristics. A trench depression sidewall dielectric is formed, and the trench is filled with a transistor silicon material by a selective epitaxial process. Base and emitter region are then formed in the collector epitaxial material.

Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously. This architecture allows propagation delays between devices to be determined. A driving device (264) toggles its input on a first clock edge. On a subsequent clock edge, the receiving circuit (266) samples its input.

Abstract: A Zener diode structure comprising a semiconductor substrate layer of a first conductivity type, a first epitaxially formed semiconductor layer of the first conductivity type disposed on the substrate layer, a second epitaxially formed semiconductor layer of a second conductivity type disposed on the first semiconductor layer, a third semiconductor layer of the first conductivity type disposed over the second semiconductor layer, a buried layer of the first conductivity type disposed between and contacting the second and third semiconductor layers and a semiconductor contact region of the second conductivity type extending between and contacting a surface of the third semiconductor layer and the buried layer, the semiconductor contact region being an anode of a Zener diode, the buried layer being a cathode of the Zener diode.

Abstract: A system scan path architecture is provided by a device select module (DSM) (18) which may be used in conjunction with associated circuits (16a-b) to select secondary scan paths (PATH1-m) on each circuit for coupling with a primary scan path on a test bus (14). The test bus (14) is controlled by a primary bus master (12). Remote bus masters (124) may be used in conjunction with the DSMs (18) to provide serial-scan testing independent of the primary bus master (12).

Abstract: A device having a circled array of tapered motor driven rollers center and find the flat edge of a semiconductor wafer by rotating the wafer until the flat edge is over a photo cell, at which time finder rollers secure the wafer in its centered and orientated position.