Abstract: A system scan path architecture is provided by a device select module (DSM) (18) which may be used in conjunction with associated circuits (16a-b) to select secondary scan paths (PATHl-m) on each circuit for coupling with a primary scan path on a test bus (14). The test bus (14) is controlled by a primary bus master (12). Remote bus masters (124) may be used in conjunction with the DSMs (18) to provide serial-scan testing independent of the primary bus master (12).

Abstract: A translucent hemispherical diffuser provides shadowless, uniform illumination of an object to be inspected or otherwise viewed. The optical medium of the translucent diffuser has a milk glass optical consistency, and/or one or more surfaces of the diffuser may be textured to diffuse light entering or leaving the optical medium of the diffuser. The hemispherical diffuser is placed between a light source and the object to be viewed. Light from the light source entering the optical medium of the diffuser is re-radiated uniformly from the concave surface of the diffuser. The object to be viewed is located approximately at the center of curvature of the hemispherical diffuser. Thus, the radiating concave surface of the diffuser subtends a solid angle of approximately two -pi steradians. Light may be scattered and diffused by various reflecting surfaces external to the diffuser, prior to entering the optical medium of the diffuser.

Abstract: A method of preventing forward biasing of PN junctions in junction isolated semiconductor devices to prevent parasitic transistor action. A biasing element is connected to the substrate/isolation regions to switch the regions to a low potential. The method is particularly well suited for implementation in the new multi-epitaxial semiconductor processes and structures.

Abstract: A method and apparatus is disclosed for the non-destructive measurement of die-attach quality in packaged integrated circuit. The apparatus is used in a production line and uses acoustical pulses to generate signals from within the integrated circuit indicative of the die-attach quality.

Abstract: A circuit (90) converts a true ECL signal to a true TTL signal. The circuit includes a differential circuit (180) that receives an ECL signal having high and low values. The differential circuit produces a differential signal therefrom that has a high value in response to one of the high and low values of the true ECL signal, and a low value in response to the other of the high and low values of the true ECL signal. A first translator circuit (36, 64) has an input (32) coupled to the differential circuit (180). The first translator circuit (36, 64) transmits a true low TTL output (56) signal having a voltage level referenced to the voltage level of a TTL low supply voltage in response to receiving a high value of the differential signal. A second translator circuit (46, 52) has an input (38) and is coupled to a TTL high supply voltage and the output (56).

Abstract: Division and square root calculations are performed using an operand routing circuit (16) for receiving an operand N, and operand D and a seed value S and directing the operands and seed value to a multiplier (38). Single multiplier (38) is configured into two arrays for calculating partial products of N and S and D and S. The results of multiplier (38) are transmitted through switching circuitry (20) or registers (48) (50) either to operand routing circuitry (16) or adder (44) depending on a convergence algorithm. The final result is rounded.

Abstract: A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames and strips, represents an ideal pattern as one or more polygons. Each polygon's data description is contained within a single data frame. The database is transformed into a turnpoint polygon representation, then a left and right vector representation, then an addressed pixel representation, then a bit-mapped representation of the entire target. Most of the transformations are carried out in parallel pipelines. Guardbands around polygon sides are used for error filtering during inspection. Guardbands are polygons, and frames containing only guardband information are sent down dedicated pipelines. Error filtering also is done at the time of pixel comparisons of ideal with real patterns, and subsequently during defect area consolidation.

Abstract: A vacuum-tight wafer carrier, and a load lock suitable for use with this wafer carrier. The wafers are supported at each side by a slightly sloping shelf, so that minimal contact (line contact) is made between the wafer surface and the surface of the shelf. This reduces generation of particulates by abrasion of the surface of the wafer. The carrier also contains elastic elements to restrain the wafers from rattling around, which further reduces the internal generation of particulates. When the wafer carrier is placed into the load lock, its body is lowered from beneath its cover through an aperture into a lower chamber, where wafers are loaded and unloaded under vacuum; the carrier cover remains covering the aperture into the lower chamber, so that the wafers never see any surface which is directly exposed to atmosphere. A wafer transport arm mechanism permits interchange of wafers among one or more processing stations and one or more load locks of this type.

Abstract: A reference time signal generation system 10 is provided which comprises a phase lock loop circuit 12 which generates a reference voltage V.sub.m. The phase lock loop circuit 12 comprises first and second divider circuits 14 and 18 coupled to the input of a phase comparator 16. The output of the phase comparator 16 is coupled to a loop filter 20 which generates a DC representation of the phase differential of the inputs of the phase comparator 16. The output of the loop filter 20 is input into a bias generator 26. The output of the bias generator 26 is coupled to the input of a voltage controlled oscillator 28 which has its output coupled to the input of second divider circuit 18. The reference voltage signal V.sub.m is taken from the output of the bias generator 26 and is transmitted to remote timing elements 32, 34 and 36 where it may be used to create reference timing signals which will accurately track the reference clock signal input into phase lock loop circuit 12.

Abstract: A carrier for use in a continuous chemical vapor deposition reactor system has a lid with tapered edges which match the sides of a recess in the carrier in which the lid resides during processing of the semiconductor to provide a precise fit for the lid and to minimize thermal stresses in the carrier, the lid and the lid-carrier assembly due to extreme heat during processing of the semiconductor wafer.

Abstract: A sense amplifier (38) uses a current source (40) to pull-up a product line (14) during as low-to-high transition. After a desired voltage is reached on the product line (14), the current source is turned off by a delay feedback circuit (44). A hold-up circuit (42) holds the product line at the desired voltage until a high-to-low transition occurs.

Abstract: A semiconductor module that densely packs integrated circuit chips to provide electronic systems or large memory modules in an array of stacked silicon boards. The semiconductor chips may be flip mounted and the back side of each chip is in thermal contact with an adjacent silicon board to provide heat conduction away from the chip.

Abstract: A first polysilicon layer (18) is initially deposited onto a layer of field oxide (16). A dielectric (26) is formed on a portion of the first polysilicon layer (18). A second polysilicon layer (28) is deposited over the dielectric (26) and the first polysilicon layer (18). After the selective deposition of a mask (30) on to the second polysilicon layer (28), the polysilicon layers (18, 28) are anistropically etched to form a polysilicon to polysilicon capacitor (34) and a contact (36) of the capacitor (34). The dielectric (26) functions as an insulator for the capacitor (34) and as a barrier during anisotropic etching for protecting the underlying polysilicon layer (18).

Abstract: There is disclosed a circuit and method for converting on/off logic signals from one medium to on/off signals useful in a different medium. The circuit is particularly adapted to translate from positive voltage levels to negative voltage levels. The circuit includes voltage control levels for precisely controlling voltage as a function of temperature, all while only using positive voltage levels on the conversion circuit.

Abstract: A process of fabricating semiconductor devices involving plural epitaxial layer growth steps.

Abstract: A timing system using shared address generator(s) to address memories that form the basis of each pin's timing reference generator can reduce the amount of hardware required to implement a "Timing Generator Per Pin" architecture in a VLSI tester by at least 50%.

Abstract: A method and apparatus for correcting errors in a thermometer code data array (32). A parallel A/D converter (22) comprises an array (26) of comparators and an encoder (30). The correction of errors in the data array (32) produced by the comparators (26) is accomplished by an array (24) of majority error correction gates which is placed between the array (26) of comparators and the encoder (30) in the A/D converter (22).

Abstract: A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames and strips, represents an ideal pattern as one or more polygons. Each polygon's data decription is contained within a single data frame. The database is transformed into a turnpoint polygon representation, then a left and right vector representation, then an addressed pixel representation, then a bit-mapped representation of the entire target. Most of the transformations are carried out in parallel pipelines. Guardbands around polygon sides are used for error filtering during inspection. Guardbands are polygons, and frames containing only guardband information are sent down dedicated pipelines. Error filtering also is done at the time of pixel comparisons of ideal with real patterns, and subsequently during defect area consolidation.

Abstract: There is disclosed a circuit and method for converting on/off logic signals from one medium to on/off signals useful in a different medium. The circuit is particularly adapted to translate from negative voltage levels to positive voltage levels. The circuit includes voltage control levels for precisely controlling voltage as a function of temperature, all while only using positive voltage levels on the conversion circuit.

Abstract: This disclosure describes a plating fixture to hold a silicon wafer containing integrated circuits in a metal plating bath. The wafer is coated with photoresist to a thickness equal to the desired bump height and the desired bump locations patterened by standard photolithographic techniques. The wafer is then loaded in the fixture and the fixture placed in the plating bath so that the patterned side of the wafer is facing up and the plating anode is located directly above the wafer. Systems presently on the market have the wafer positioned with the patterned side facing down and the anode located below it, or the wafer faces sideways and the anodes are access from it. These present systems allow air to be entrapped in the pattern of the photoresist, lowering yield by under plating or uneven plating of the bumps on the wafer. This disclosure prevents such yield loss and also allows cleanups on the wafer after it is loaded in the fixture.