Abstract: A process for the formation of pillars (28) in connection with the fabrication of a semiconductor device (10) is disclosed. The process first aligns a lead pattern (30) with an existing structure (24) in the semiconductor device (10). Next, the process aligns a pillar pattern (32) with the lead pattern (30). These two patterns (30, 32) are then transferred downward into respective conductive layers (26, 28) of the semiconductor device (10). An insulating layer (34) is deposited over the conductive layers (26, 28) and etched-back to expose a portion of the pillar (28). A conductive layer (42) is applied over the exposed pillar (28).

Abstract: A reconfigurable resource architecture enhances a test system's utilization by allowing product-mix dependent allocation of test system resources. The test system resources can be configured to test several device types with different pin counts simultaneously. The configuration can be changed to accommodate various product mixes based on pin count.

Abstract: A method of making a merged bipolar and field effect semiconductor transistors on a semiconductor substrate by forming a diffused buried DUF collector region of a second conductivity type in the substrate, and growing an impurity doped epitaxial layer of silicon of the second conductivity type over the substrate. Once the epitaxial layer is grown, a plurality of isolation regions are formed in this layer. A bipolar transistor is formed over the DUF region in a bipolar isolation region and a field effect transistor formed in the second isolation region. Contacts and interconnects are deposited and patterned.

Abstract: A test configuration register (80) associated with a programmable memory device (88), wherein the signals at the outputs of the test configuration register force elements of the memory device into certain logic states to enable the device to be tested without programmning the device's logic array (22).

Abstract: Described is an architecture for translating between ECL and TTL/CMOS signal levels in which the control signal applied to the translating circuitry is of the same type as the output signal of the device in which the architecture is used.

Abstract: A slice handling apparatus (10) is mounted on a robot arm (12) to provide automated processing of semiconductor slices (69). The slice handling apparatus (10) has three tines, a center tine (50) and two side tines (62). The side tines (62) are fixed to position, while the center tine (50) is moved in and out using a control field actuator (20). A Hall effect sensor (26) on the control field actuator (20) provides an electrical feedback to provide a firm gripping force with reduce damage to slice edges by sensitive control of the gripping force. The tines (50, 62) have locator pins (58) which hold the slice (69). The locator pins (58) have a tapered bottom portion (84) and a vertical holding portion (86). The tapered bottom portion (84) prevents the slice (69) from contacting the tines (50, 62) in the event that the slice handling apparatus (10) is not positioned at the exact vertical position desired.

Abstract: A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames and strips, represents an ideal pattern as one or more polygons. Each polygon's data description is contained within a single data frame. The database is transformed into a turnpoint polygon representation, then a left and right vector representation, then an addressed pixel representation, then a bit-mapped representation of the entire target. Most of the transformations are carried out in parallel pipelines. Guardbands around polygon sides are used for error filtering during inspection. Guardbands are polygons, and frames containing only guardband information are sent down dedicated pipelines. Error filtering also is done at the time of pixel comparisons of ideal with real patterns, and subsequently during defect area consolidation.

Abstract: A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames and strips, represents an ideal pattern as one or more polygons. Each polygon's data description is contained within a single data frame. The database is transformed into a turnpoint polygon representation, then a left and right vector representation, then an addressed pixel representation, then a bit-mapped representation of the entire target. Most of the transformations are carried out in parallel pipelines. Guardbands around polygon sides are used for error filtering during inspection. Guardbands are polygons, and frames containing only guardband information are sent down dedicated pipelines. Error filtering also is done at the time of pixel comparisons of ideal with real patterns, and subsequently during defect area consolidation.

Abstract: A fuse link (50) is formed using a method which offers greater scalability of the general conductor system used to wire the device. An oxide mask (36) having the shape of a desired fuse link is formed over a thin metallization layer (34). A barrier layer (38) is formed over the thin metallization layer (34). A conductive layer (40) is formed over the barrier layer (38). A photoresist mask (42) supplied to the conductive layer (40), and the conductive layer is etched to formed interconnects (44, 46). Subsequently, the barrier layer (38) and thin metallization layer (34) are etched, thus rendering a fuse link (50) between interconnects (44, 46) under the oxide mask (36).

Abstract: A wire bonder for bonding semiconductor packages that require a deep access to bond between the semiconductor device bond pads and the bonding area on the package to avoid interference between the bond head and the package pins, the bonder including a bellows actuated wire clamp, a reverse venturi to remove slack from the bonding wire, and a lengthened bonding tool.

Abstract: Conversion from a first set of logic levels, such as ECL levels, to a second set of logic levels, such as TTL, is performed by using a regulator (46) and is parallel to the circuit generating the first set of logic levels.

Abstract: An automatic test pattern generator and process assigns value-strength number to selected nodes representing the electrical characteristic strength of integrated circuits including field effect transistors and the logic state values at those nodes. These value-strength numbers become sensitized to the inputs of the selected node and become propagated to outputs of the selected node for establishing patterns for test signals. The test signals later become used in chip testers for determining good and bad integrated circuit chips. The value-strength numbers also become used in dynamic testing of the integrated circuit nodes by using clock signals of the integrated circuit to establish a transition at a start node of a test path. Within a known clock period later, the transition should become captured at an end node of the test path.

Abstract: A method of backside damaging a silicon semiconductor wafer by abrading the wafer in an abrasive powder is disclosed. The wafer is rotated or translated in the powder while the powder is being vibrated. A fixture holds one or more semiconductor wafers during the processing and allows the wafer to be rotated during processing if desired.

Abstract: An output driver is provided for an IC (14, 16 and 18) to drive a data bus (12) connected thereto. The output driver may include a push-pull configuration comprising both a P and N channel transistor (78 and 80, respectively). A switching network of transistors (86, 88, 90, 92 and 94) is included to prevent loading of the output signal, V.sub.out when the power supply voltage, V.sub.cc is inactive. More particularly, the backgate of P channel transistor (78) is coupled to V.sub.out when V.sub.cc is inactive and coupled to V.sub.cc when V.sub.cc is active.

Abstract: The present invention provides a method, and a product made by the same, of fabricating an NPN bipolar transistor of a novel design simultaneously with the fabrication of double polysilicon CMOS/FAMOS devices, on an integrated circuit device. N wells 14 and 16 for the NPN transistor and the PMOS device are fabricated simultaneously. P type material is implanted to form the voltage adjust implant layer 19 of the FAMOS structure, and the base layer 18 of the NPN bipolar transistor, in the same process steps. In the process steps of forming the floating gate structure 36 of the FAMOS transistor, a polysilicon region 34 is also formed on the NPN transistor site. This polysilicon region 34 serves as a self-aligned implant mask during the implant of the base regions 88 of the NPN transistor. N type material is implanted in the same process steps to form the source and drain regions 66 of the FAMOS transistor and the emitter region 64 of the NPN transistor.

Abstract: A circuit technique for biasing a complementary NPN-PNP Darlington Emitter Follower Stage without additional biasing resistors or current sources. Four diode-connected transistor are connected in series to provide biasing across the Darlington. Two transistors, one NPN and one PNP, are added with their bases and emitters connected in parallel with the top and bottom diodes, respectively, forming two current mirrors. The collector of the NPN transistor connects to the emitter of the first Darlington NPN transistor. The collector of the PNP transistor connects to the first Darlington PNP transistor. The current mirrors provide equal current to the two first Darlington transistors. These currents are also equal to the current through the four diodes for identically sized transistors.

Abstract: In semiconductor vacuum processing, it is desirable to minimize the material handling mechanisms that must be located in the evacuated process chamber. To accomplish this, a mechanism has been designed that locates the necessary power elements such as motors (12-16) outside the chamber (32). Power is transmitted to the mechanism via commercially available rotary vacuum feed-through devices (30) mounted in the chamber walls (28) and the separable, zero backlash couplings (44) located within the chamber. These couplings (44) allow easy removal and replacement of the handling mechanism without the need for physical access and tools.

Abstract: A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames and strips, represents an ideal pattern as one or more polygons. Each polygon's data description is contained within a single data frame. The database is transformed into a turnpoint polygon representation, then a left and right vector representation, then an addressed pixel representation, then a bit-mapped representation of the entire target. Most of the transformations are carried out in parallel pipelines. Guardbands around polygon sides are used for error filtering during inspection. Guardbands are polygons, and frames containing only guardband information are sent down dedicated pipelines. Error filtering also is done at the time of pixel comparisons of ideal with real patterns, and subsequently during defect area consolidation.

Abstract: A boundary test architecture for use in an integrated circuit (10) comprises input and output test registers (12, 22) having functions controlled by an event qualifying module (EQM) (30). The EQM (30) receives a signal from the output test register (22) indicating that a matching condition has been met. In response to a matching condition, EQM (30) may control the input and output test registers (12, 22) to perform a variety of tests on the incoming and outgoing data. During testing, the internal logic (20) may continue to operate at-speed, thereby allowing the test circuitry to detect faults which would not otherwise be discoverable. A memory buffer (64) may be included to store a plurality of input data for test data.

Abstract: A distributed electron cyclotron resonance remote plasma processing apparatus and method which includes generating electron cyclotron resonance activated species in plasma formation regions distributed peripherally around, remote from the wafer processing chamber and in fluid communication with the main transfer chamber; containing the activated species using a microwave gas discharge and a magnetic field in the plasma formation regions; introducing the plasma streams to the main transfer chamber; creating a magnetic mirror in the main transfer chamber using a magnetic field; and introducing the species to the process chamber and to a face of the workpiece. Such an apparatus could use multiple energy/excitation sources.