Abstract: A circuit for generating a data I/O control signal used in a semiconductor memory apparatus comprises a delay block for generating a delay signal having a relatively short delay value and a delay signal having a relatively long delay values, and a selection block for selecting any one of the delay signals according to an operational mode. The selection block selects an output signal of the first delay unit in a high-speed operation mode and selects an output signal of the second delay unit in a low-speed operation mode.

Abstract: A bit line equalizing control circuit of a semiconductor memory apparatus includes a control signal generating unit that receives a bank active signal to generate a control signal such that a bit line equalizing signal is delayed and enabled, a bit line equalizing selecting unit that generates a bit line equalizing detection signal in response to a plurality of mat select signals and the control signal, and a driver that receives the bit line equalizing detection signal to generate the bit line equalizing signal.

Abstract: Methods and catalysts for producing alcohols, ethers, and/or alkenes from alkanes are provided. More particularly, novel caged, or encapsulated, metal oxide catalysts and processes utilizing such catalysts to convert alkanes to alcohols and/or ethers and to convert alcohols and/or ethers to alkenes are provided.

Abstract: A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate an internal data strobe clock signal, a timing discriminating block configured to discriminate toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal to generate a timing discrimination signal, and an enable controlling block configured to generate the buffer enable signal in response to the timing discrimination signal.

Abstract: A phase-change memory device and a method of manufacturing the same, wherein the phase-change memory device includes a semiconductor substrate having a switching device, a phase-change layer formed on the semiconductor substrate having the switching device to change a phase thereof as the switching device is driven, and a bottom electrode contact in contact with the switching device through a first contact area and in contact with the phase-change layer through a second contact area, which is smaller than the first contact area.

Abstract: A multiple path stereoscopic projection system is disclosed. The system comprises a polarizing splitting element configured to receive image light energy and split the image light energy received into a primary path and a secondary path, a reflector in the secondary path, and a polarization modulator or polarization modulator arrangement positioned in the primary path and configured to modulate the primary path of light energy. A polarization modulator may be included within the secondary path, a retarder may be used, and optional devices that may be successfully employed in the system include elements to substantially optically superimpose light energy transmission between paths and cleanup polarizers. The projection system can enhance the brightness of stereoscopic images perceived by a viewer. Static polarizer dual projection implementations free of polarization modulators are also provided.

Abstract: A semiconductor integrated circuit includes a sense amplifier for sensing input data and a sense amplifier controller for blocking a signal path between the sense amplifier and a memory cell when a test mode signal is activated.

Abstract: A test circuit that senses a misaligned probe during a test includes a first power control section that senses voltage levels of a plurality of sensing lines and controls power supplied to a lower circuit section provided below a part of a pad group, and a second power control section that selectively provides an internal voltage in response to a sensing result of the first power control section.

Abstract: An input circuit is disclosed. The input circuit can include a cross voltage generating block that can be configured to perform charge-sharing on a pair of input signals whose phases are opposite to each other and generate a cross voltage, and an input buffer block that can be configured to buffer the pair of input signals at a voltage level corresponding to a voltage level of the cross voltage and generate an output signal.

Abstract: A current driving apparatus and method using a pulse width modulation (PWM) technique to display a desired gray level for passive matrix organic light emitting diode (PMOLED) display applications is disclosed. The current driving circuit includes a memory, a logic and a segment driver. The memory stores a desired gray level, the logic comprises a counter and provides a predetermined bias time, and the segment driver provides a constant current to the PMOLED display based on the desired gray level and the predetermined bias time. The segment driver provides a constant current to the PMOLED display until the counter value reaches the desired gray level, and the counter is first counted zero for the predetermined bias time and then increments by one for every other cycle.

Abstract: Disclosed is a semiconductor integrated circuit that allows a fail path to be detected. A semiconductor integrated circuit as described herein can be configured to include a data register that can receive input data to generate and store a write expectation value and a read expectation value, during a period in which a test mode is activated, a first comparing unit that compares write data written in a memory cell with the write expectation value, and a second comparing unit that compares read data read from the memory cell with the read expectation value.

Abstract: The present invention provides an electronic message management system (EMS) that includes a real-time feedback loop where data is collected from the electronic messages on incoming connection attempts, outgoing delivery attempts, and message content analysis, and written to a centralized data matrix. A separate process accesses the data matrix and analyzes trends in that data. The detected data patterns, trends or behavior is based on configuration parameters for the recipient. Based on these determinations, the process is able to instruct components in the EMS to accept, redirect, refuse, modify, defer, or otherwise dispose of the connection request, the delivery attempt, or the message. Associated methods for managing the transmission of electronic messages are also disclosed.

Abstract: An overlay mark arrangement for reducing the asymmetric profile and an overlay shift during an integrated circuit manufacturing process is disclosed. In one embodiment, the overlay mark arrangement may comprise a first mark, a second mark and a stress releasing means. The first mark is used to indicate the position of a lower layer, the second mark is used to indicate the position of an upper layer; and the stress releasing means is used to release the film stress induced by the upper layer. Unlike the conventional overlay mark arrangements, which will have a severe overlay mark shift due to the film stress, the asymmetric overlay mark profile can be improved by using multiple trenches around the overlay marks according to certain embodiments of the invention disclosed herein.

Abstract: A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.

Abstract: Disclosed are systems and methods for preventing unauthorized persons from using an electronic device within a facility. In such an embodiment, the system may include a plurality of RFID tags each having unique identification information associated with a wearer of one of the RFID tags. This system may also include an RFID reader associated with the electronic device and having an RFID coverage zone for detecting RFID tags within the coverage zone. A device management system may be connected to the reader and configured to determine whether wearers in the coverage zone are authorized to use the electronic device based at least in part on detected RFID tags' unique identification information. In such an embodiment, the device management system is configured to activate the electronic device if it determines only authorized wearers are detected in the coverage zone, and to deactivate the electronic device if it determines an unauthorized wearer is detected in the coverage zone.

Abstract: A power noise detecting device includes a plurality of power lines, and a power noise detecting part configured to detect power noise by rectifying voltages of the plurality of power lines and converting the rectified voltages into effective voltages.

Abstract: An HDL description of a communications protocol machine for transforming object communications into low-level octet sequences for physical transport is synthesized onto a programmable logic device such as an FPGA. This communications protocol machine replaces traditional software-based inter-ORB protocol engines in distributed computing environments, including embedded environments, to provide reduced latency. The communications protocol machine is described with two distinct elements: a protocol messaging machine and an encoder/decoder. The protocol messaging machine converts an object communication into a low-level octet sequence comprising one or more inter-ORB protocol messages and converts a low-level octet sequence comprising an inter-ORB protocol message into an object communication.

Abstract: A semiconductor integrated circuit includes a row main signal generation section configured to provide a row main signal serving as a driving reference for a plurality of row-series circuit units in response to a bank active signal, wherein activation timing of the row main signal is controlled by a test mode signal.

Abstract: A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers.

Abstract: A phase detecting circuit includes a first node that outputs a pull-up control signal, a second node that outputs a pull-down control signal, an initializing unit that initializes voltage levels of the first and second nodes in response to a pre-charge signal, a data input unit to which receives a receiver data, a phase comparison unit that compares a phase of a receiver clock and a phase of the receiver data input to the data input unit to control the voltage levels of the first and second nodes, and a charging/discharging unit that charges or discharges electric charges that are applied to the first and second nodes.