Patents Represented by Attorney, Agent or Law Firm Beall Law Offices
  • Patent number: 6034962
    Abstract: In a method of increasing the network use efficiency of computer communication and reducing the limitation of byte stream in a transmit/receive request, a virtual circuit is established between protocol modules such as applications for providing the communication function between software to mate one transmit request with one receive request. By returning an acknowledgement in a unit of request, any vain acknowledgement can be avoided and even in the case of asynchronous transmission/reception, a request which is completed in transmission/reception can be ended immediately, thus permitting efficient data transfer. Even when the transmit request length and the receive request length differ from each other, reliable communication of a request having a smaller request length can be ensured between mating transmit and receive requests.
    Type: Grant
    Filed: October 3, 1997
    Date of Patent: March 7, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Ryuichi Ohno, Mitsuo Asai, Hirofumi Yamashita, Yoshihiro Takiyasu
  • Patent number: 6032858
    Abstract: In an electronic money storing apparatus in an electronic money transaction system for transmitting and receiving electronic money between electronic money cards holding electronic money, IC cards are loaded to each of a plurality of IC card read/write unit connected to a controller. Each of the IC cards holds electronic money and transmits and receives electronic money with another IC card in the electronic money transaction system. The controller reads and writes the electronic money of the IC cards loaded to a selected IC card read/write unit and transmits and receives the electronic money between that IC card and an electronic money storing media the external of the electronic money storing apparatus.
    Type: Grant
    Filed: May 29, 1997
    Date of Patent: March 7, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Kazuyuki Yazumi, Manabu Hayashi, Hitoshi Maekawa
  • Patent number: 6035381
    Abstract: A data memory unit including a main memory data storage portion that is accessed by a row address and a column address representing all of the bits of a given address and a main memory key data storage portion that is accessed by just the row address which is fewer that all of the bits of the given address are integrated into a single semiconductor chip. A data storage apparatus is composed of a plurality of such data memory units. The main memory key data storage portion can be increased at the same time as when the capacity of the main memory is increased, thereby simplifying the process of increasing main memory size.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: March 7, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Kimiko Mita, Atsushi Tanaka
  • Patent number: 6033792
    Abstract: A recording head for recording data onto a recording medium is provided with a thin film formed of the following compound Fe.sub.100-a-b-c X.sub.a Y.sub.b Z.sub.c, wherein X is at least one element selected from the group consisting of Nb, Ta, Hf and Zr, Y is one or two elements selected from the group consisting of Cr, Ru, Al, Si, Ti and Rh, and Z is at least one element selected from the group consisting of C and N, and wherein 5.ltoreq.a.ltoreq.20, 0.5.ltoreq.b.ltoreq.15, 1.ltoreq.c.ltoreq.20, and 0.5.ltoreq.a/c.ltoreq.0.7, the carbide or the nitride of the element X having an average grain size of not larger than 3 nm. This way, increased corrosion resistance is provided without substantially reducing magnetic characteristics such as saturation and coercive force. A recording apparatus, such as a VTR, including such a recording head is disclosed as well as a recording medium formed using this thin film.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: March 7, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Fumiyoshi Kirino, Shigekazu Otomo, Nagatugu Koiso, Noriyuki Kumasaka, Takeshi Miura
  • Patent number: 6034912
    Abstract: A memory portion and a logic circuit portion of a semiconductor device are formed on a single semiconductor substrate in which a first logic circuit block and a second logic circuit block are formed in different areas and the second logic circuit is located between a pair of memory blocks. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block. A clock signal entered at the center portion of the semiconductor chip is supplied to a plurality of first state clock distributing circuits equidistantly disposed from the center portion and then to a plurality of second stage clock distributing circuits at least equidistantly disposed from each of the first state clock distributing circuits.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: March 7, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Isomura, Atsushi Shimizu, Keiichi Higeta, Tohru Kobayashi, Takeo Yamada, Yuko Ito, Kengo Miyazawa, Kunihiko Yamaguchi
  • Patent number: 6032857
    Abstract: An electronic money system has an IC card for electronic money having a memory for maintaining money deposit and money debit information and another memory, such as an EPROM, for storing transaction data, including detailed information of transactions, such as the content of a typical receipt received from a retail store. The transaction information can be used at a later time in a personal computer so that an electronic record of household expenses can be maintained The transaction data that is stored includes the product name, price of the product, quantity of the product purchased and similar details of the transaction. The IC card memory can record the name and telephone number of a retail store where the card has been used or a network address can be recorded in the memory for use by a customer to access electronic direct-mail information by using a PC.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: March 7, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Hiroki Kitagawa, Yo Miyamoto, Jun Furuta, Masaki Takano, Takashi Matsubara, Takao Ohsawa
  • Patent number: 6032124
    Abstract: A workflow system comprising a plurality of workflow subsystems connected to a LAN (Local Area Network), these workflow subsystems being composed of servers and clients, and provides a workflow system which permits an integrated management of the definitions of the business processes placed under decentralized management, through the server managing shipping documents, BPs (Business Processes) describing shipping routes of shipping documents in the subsystem, and business process connection data to connect the BPs.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: February 29, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Saito, Shunsuke Akifuji, Hiroshi Tsuji, Hiroshi Majima, Tetsuji Toge
  • Patent number: 6032263
    Abstract: A disk array stores data records and parity records. The data records are transferred to the disk array through a control unit that is connected to a host processor. The disk array is part of a disk unit having a processor for generating parity records from information sent by the control unit to the disk unit. The parity record is generated and stored in the disk unit to reduce the number of data transfer operations between the control unit and the disk unit for storage systems using disk array disk units.
    Type: Grant
    Filed: May 13, 1998
    Date of Patent: February 29, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Toshihiko Tamiya, Hisashi Takamatsu, Akira Kurano, Hirofumi Inomata
  • Patent number: 6032157
    Abstract: For retrieving attribute information through image information which is not linked with the attribute information: displaying on a display screen the first image information corresponding with attribute information and second image information that has a common attribute with the first image information; and storing a correspondence between the first image information and the second image information in response to an input of an instruction to confirm the correspondence between the first image information and the second image information, and retrieving and displaying the attribute information on the basis of the stored correspondence between the first image information and the second image information as well as correspondence information between the first image information and the attribute information, in response to an input for object choice indicated by the second image information.
    Type: Grant
    Filed: June 24, 1998
    Date of Patent: February 29, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Maki Tamano, Hiroyuki Okuda, Hiroshi Yajima, Tadashi Hirose, Noritugu Kagaya
  • Patent number: 6031257
    Abstract: In a CMOS gate array, each of bonding pads corresponding to input cells for signals and bonding pads corresponding to input cells for supply voltages is formed of a plurality of conductor layers, whereas each of bonding pads (non-connected pads) corresponding to input/output cells not to be used is formed of, for example, the uppermost conductor layer. Thus, the bonding pad (non-connected pad) corresponding to the input/output cell not to be used becomes greater in the thickness of an underlying insulator film and longer in its spacing from a semiconductor substrate in comparison with each of the bonding pad for the signal and the bonding pad for the supply voltage.
    Type: Grant
    Filed: June 11, 1998
    Date of Patent: February 29, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Noto, Eiji Oi, Yahiro Shiotsuki, Kazuo Kato, Hideki Ohagi
  • Patent number: 6031863
    Abstract: The wireless LAN system has an information-carrying capacity which is several times the transmission rate obtained by a single cell. The wireless LAN system properly notifies hopping information even if an error in transmission arises. Hopping control is carried out on a master base-station device 10a and slave base-station devices 10b and 10c based on a synchronizing frame generated from hopping timing of the master base-station device 10a. After completion of the hopping control, each base-station device 10 starts to send hopping information to radio terminals 2 present in the same cell. Radio terminals 2, which are in the same cell as one of the base stations 10, work under the base-station device 10.
    Type: Grant
    Filed: March 19, 1996
    Date of Patent: February 29, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Hidehiko Jusa, Masaaki Shida
  • Patent number: 6032265
    Abstract: A fault-tolerant computer system, which prevents an I/O fault from reaching the CPU block while using an alternative I/O block to continue processing, employs common general-purpose processors with a minimum of specialized peripheral circuits. Dual system bus adapters are provided not in the fast-operating CPU portion requiring sophisticated packaging technology, but in the low-speed interface between the CPUs and the I/O bus adapters. This allows the CPUs and I/O bus adapters to be shared by ordinary data processors, workstations, or personal computers while implementing a fault-tolerant computer system. If a one-shot hardware fault occurs in a CPU or in an I/O bus adapter, the faulty component is disconnected from the system so that the system will operate uninterruptedly.
    Type: Grant
    Filed: July 18, 1996
    Date of Patent: February 29, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Oguro, Shinichiro Yamaguchi, Yoshihiro Miyazaki, Soichi Takaya, Masataka Hiramatsu, Nobuo Akeura
  • Patent number: 6028906
    Abstract: The present invention relates to a control rod installed in a boiling water reactor (BWR), and particularly to a control rod using metal. An object of the present invention is to provide a manufacturing method of a control rod for a boiling water reactor, having excellent corrosion resistance in high temperature water and excellent wear resistance at the time of fabrication, and in which the influence of the manufacturing process is slight. In order to achieve the above described object, the present invention provides a manufacturing method of a control rod for a boiling water reactor constructed with sheaths having a U-shaped cross section attached to each end of a tie rod having a cruciform cross section, and rod, plate or oval tube cross section metal hafnium type neutron absorber material contained inside the sheaths, in which an anodized film is provided on a surface of the neutron absorber material as a pre-process of assembly of the neutron absorber material in the structure of the control rod.
    Type: Grant
    Filed: August 17, 1998
    Date of Patent: February 22, 2000
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Norio Kawashima, Yasuyuki Gotoh, Akira Koizumi, Kouichi Machida, Yoshiharu Kikuchi, Takayoshi Yasuda, Yoshitaka Nishino
  • Patent number: 6028833
    Abstract: An optical disk signal processing apparatus retains compatibility with the conventional continuous servo recording technique, and reduces the amount of noise included in a signal played back from the optical disk without the need to decrease the size of the area for recording data, resulting in a drastically increased signal-to-noise ratio. The optical disk signal processing apparatus has a light source, an optical system for leading a light beam generated by the light source, an optical device for converging the light beam output by the optical system and applying the converged beam to the rotating optical disk, a signal detecting optical system for detecting a signal reflected by the rotating disk through the optical device, and a light detecting instrument for converting light produced by the signal detecting optical system into an electrical signal and a data detecting circuit.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: February 22, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Maeda, Hisataka Sugiyama
  • Patent number: 6028360
    Abstract: The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: February 22, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Nakamura, Tsuyoshi Tamaru, Naoki Fukuda, Hidekazu Goto, Isamu Asano, Hideo Aoki, Keizo Kawakita, Satoru Yamada, Katsuhiko Tanaka, Hiroshi Sakuma, Masayoshi Hirasawa
  • Patent number: 6025974
    Abstract: A magnetic head slider assembly for a magnetic disk type recording/reproducing apparatus includes a slider body, a sliding pad provided on the slider body and projecting beyond a disk facing surface thereof, a thin film layer disposed at one end of the slider body, a magnetic head constituted by the thin film layer as an integral part thereof, and a core pad projection incorporating therein a core of the magnetic head and projecting beyond an adjacent disk facing surface of the slider body. The sliding pad is provided at a region of the slider body ahead of the core pad projection and prevents generation of a floating force by making use of a relative movement between the slider body and the magnetic disk.
    Type: Grant
    Filed: February 10, 1999
    Date of Patent: February 15, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Mikio Tokuyama, Teruyoshi Higashiya, Yoshinori Takeuchi, Sadanori Nagaike, Kazuo Nate, Tetsuji Higashijima, Shinsuke Higuchi, Shigeo Nakamura, Kenji Mori
  • Patent number: 6026368
    Abstract: Prioritized queues of advertising and content data are generated by a queue builder and sent to an on-line queue manager. A computer mediated communications network provides content and subscriber data to the queue builder and receives content segment play lists from the on-line queue manager. An exposure accounting module calculates and stores information about the number of exposures of targeted material received by subscribers and generates billing information. An information warehouse manager is employed to receive data from advertisers' data bases and third party sources as well as from the computer mediated communications network.
    Type: Grant
    Filed: July 17, 1995
    Date of Patent: February 15, 2000
    Assignee: 24/7 Media, Inc.
    Inventors: Yale Robert Brown, Matthew Brown Walker
  • Patent number: 6026394
    Abstract: A database management system for executing database operations in parallel by a plurality of nodes and a query processing method are described. The database management system contains a decision management node for deciding a distribution node for retrieving information so as to analyze a query received from an application program, generate a processing procedure for processing the query, and execute the process, and a join node for sorting, merging, and joining the information retrieved by the distribution node. When the query process is executed, the distribution node decided by the decision management node retrieves the information to be processed and the join node decided by the decision management node also obtains the result for the query from the retrieved information. The query result is outputted from an output node and transferred to the application program.
    Type: Grant
    Filed: September 4, 1998
    Date of Patent: February 15, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Masashi Tsuchida, Yukio Nakano, Nobuo Kawamura, Kazuyoshi Negishi, Shunichi Torii
  • Patent number: 6025824
    Abstract: A piezo electric transformer driving circuit and a cold cathode tube illuminating device comprising a series circuit including a switch circuit, a coil and a switching transistor and being connected successively in the named order between a power source line and a ground; a piezo electric transformer of which primary side electrode is connected to a juncture of the coil and the switching transistor; and a drive halting circuit which geneates a first control signal for turning OFF the switching circuit and further generates a second control signal for halting a switching operation of the switching transistor after a predetermined period from the generation of the first control signal, wherein the predetermined period is at least one turned ON interval of the switching transistor and through the switching operation of the switching transistor a high voltage is generated at a secondary side of the piezo electric transformer.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: February 15, 2000
    Assignees: Rohm Co., Ltd., NEC Corporation
    Inventors: Sachito Horiuchi, Eiji Nakagawa, Masanori Fujisawa, Shingo Kawashima
  • Patent number: 6022797
    Abstract: First through holes of a relatively small diameter and second through holes of a relatively great diameter are formed in proper shapes by separate processes, respectively, in a first layer insulating film. The second through holes are tapered toward a layer underlying the first layer insulating film. First, the first through holes are formed in the first layer insulating film, the first through holes are filled up with plug electrodes, and the second through holes are formed in the first layer insulating film. When filling up the first and the second through holes formed in the first layer insulating film with plug electrodes, a first conductive film deposited over the first layer insulating film is etched back to fill up the first through holes with the plug electrodes, and then etch back residues remaining on the side walls of the second through holes are removed.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: February 8, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Shigeo Ogasawara, Shigeru Takahashi, Noriaki Oka, Tadayasu Miki, Masahito Hiroshima