Abstract: A fast-discharge switch is controlled by a comparator sensing the voltage difference between the output node and the input node of a driving integrator stage that controls the slew-rate of a power switching output transistor. The fast-discharge switch turns off automatically when the output power transistor reaches (in the case of a MOS transistor) or exits (in the case of a bipolar transistor) saturation. The circuit of the invention accelerates the discharge thus reducing the turn-off delay and is insensitive of load conditions and does not affect the performance of the integrating (driver) stage that control the slew-rate.

Abstract: A circuit for the filtering of a pulse signal comprises means to detect an output pulse upon the detection of an input pulse, the shape of this output pulse being based on elementary delays obtained by the charging and discharging of capacitors. During the generation of the output pulse, no new input pulse can be taken into account.

Abstract: A monolithically integrated, transistor bridge circuit of a type suiting power applications, comprises at least one pair of IGBT transistors (M1,M2) together with vertically-conducting bipolar junction transistors transistors (T1,T2). These IGBT transistors are laterally conducting, having drain terminals (9,19) formed on the surface of the integrated circuit (1), and through such terminals, they are connected to another pair of transistors (T1,T2) of the bipolar type.

Abstract: In a 2-D graphics rendering system having a plurality of processors (PROC 0 to PROC 3) which receive instructions from a common instruction register (IR) and render polygons in a framestore (FS), in order to permit asynchronous performance of the instructions and yet ensure that overlapping polygons are properly rendered, each instruction includes an ordering code, and before writing a pixel to the framestore (FS) each processor checks that the ordering code of the polygon it is rendering is more significant than an ordering code for that pixel stored in an ordering buffer in which case the pixel is written to the framestore (FS) and the order buffer (OB) is updated, but if not the pixel is not written.

Abstract: A method for the programming of a data element in an electrically programmable memory in integrated circuit form comprising a data input/output bus, an address bus, a register for the control of instruction sequencing modes and an enable signal (/OE), said signal enabling the data output bus in an active state. When the control register receives a uniform programming instruction, it sends a uniform programming sequencing mode signal so that an inactive state of the enable signal triggers the programming of the data element at a memory address present in the address bus and so that the active state of the enable signal triggers the stopping of the programming operation. Also disclosed is an electrically programmable memory in integrated circuit form, implementing a method such as this. The disclosure can be applied to electrically programmable memories.

Abstract: A mold is disclosed for semiconductor devices intended for surface mounting, being of a type which comprises a metal plate and a body of solidified plastic resin. It consists of two plates which delimit at least one hollow adapted to receive the plate and to contain resin for forming the device body. Two elements of the mold push the plate from opposed sides against the bottom of the hollow. The hollow has two side extensions which are delimited by the side surfaces of the plate edges, thereby solidified projections are formed thereon which separate readily after the molding process. Thus, a structure is obtained wherein the plate has its bottom surface and two side edge portions fully exposed to allow optimum and controllable soldering to a printed circuit board.

Abstract: An integrated circuit unerasable memory cell which includes at least one memory cell consisting of a floating gate transistor with drain, source, and gate terminals, and a metallic shield embedded in the semiconductor substrate and covering the cell. Also provided are a diffused region defining a closed loop path on the substrate surface all around the transistor, and having said shield connected peripherally thereto in an unbroken fashion, and first and second wells extending in the substrate from the transistor to outside the diffused region, the first of said wells being connected directly to the gate terminal of the transistor. A contact inside the shield connects the shield's top surface to the cell's source. A protection diode (inside the shield) prevents charging of the floating gate during manufacture.

Abstract: A circuit for the detection of a high threshold supply voltage comprising a voltage divider and an inverter. The voltage divider is formed by a reverse-biased voltage breakdown device, such as a Zener diode, and a resistive element, such as a forward-biased transistor or a resistor. The use of the reverse-biased voltage breakdown device in the divider makes the detection threshold voltage (Vo) of the circuit stable and precise even with variations in threshold voltages due to temperature and manufacturing process variations.

Abstract: A supply-voltage-monitoring circuit, for low-power integrated circuits, in which charge-sharing through a switched-capacitor chain is used to couple the supply voltage to a dynamic sensing node. The dynamic sensing node drives a half-latch, which is stable in a no-alarm condition. In this circuit, the state of the output gets switched over in the first phase if the voltage at the terminals of the capacitor at the start of this stage (this voltage being equal to a fraction of the input voltage) crosses a determined threshold. This threshold is determined as a function of technical parameters for the construction of the circuit. These technical parameters are chiefly the threshold voltage of the transistor and the characteristics of the transistors that form the locking circuit.

Abstract: In an integrated circuit, a diode is interposed between the semiconductor substrate and the contact pad to an external bias voltage, and the substrate is biased at an internal voltage reference. Between each contact pad of the integrated circuit and semiconductor substrate, there is positioned a protection device against permanent overloads and a protection device against electrostatic discharges. By isolating the semiconductor substrate from the external voltages source and by placing a protection device between each contact pad and the substrate, a broad, general protection of the integrated circuit is obtained against all the destructive phenomena such as overloads, positive and negative overvoltages, polarity reversal and electrostatic discharges.

Abstract: A novel electrically programmable and erasable memory cell, comprising a single transistor, which is a floating gate transistor and has no selection transistor. Means are provided for establishing a high capacitive coupling between the drain and the floating gate. The capacitive coupling between the source and the floating gate is low, as is normally the case. Preferably, the control gate only partly covers the floating gate. Another part of the floating gate is covered by a semiconductor layer connected to the drain. It is the latter layer which establishes the high capacitive coupling according to the invention. Programming can then take place by the Fowler-Nordheim effect with the source under high impedance, i.e. without hot electron effect.

Abstract: The use of electromechanical devices for the configuration of the address for access to a peripheral unit in a data-processing system is avoided by replacing them with a non-volatile EEPROM-type memory. The dam in non-volatile memory is read as soon as the peripheral unit is put into operation, and the information that it delivers is stored in volatile memory and used as a comparison address to validate the operation of the peripheral unit.

Abstract: The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.

Abstract: A method for sorting the k greatest ones of a sequence of n incoming data values, by: a) sequentially writing each data value into one of n one-word memories, in a word format which includes, in decreasing weight order, the following bits: a first inhibition bit (MI), a second selection bit (MS), third data bits (MD), and fourth bits (MP) representative of the position of the incoming datum; b) setting the first bits (MI) of the n words during the arrival of the first signal; c) while writing each data value, resetting the first (MI) and second (MS) bits of the corresponding word; and d) between the arrivals of the (n-k).sup.th datum and n.sup.th datum, detecting the smallest word stored in the memories and setting its second bit (MS).

Abstract: A finger-emitter power transistor including a substrate suitable for operating as the collector of the power transistor, an epitaxial layer superimposed over the substrate (and providing a base region for the transistor), and at least one buried emitter region (for each finger of the device) below the surface of the epitaxial layer. Each buried emitter region is provided with at least one connection area to an emitter surface metallization. The connection areas between the emitter regions and their emitter surface metallization are made in various widths to provide a ballast resistance of an adequate value.

Abstract: A high-voltage switching circuit comprising two arms, wherein each arm has a P-channel load transistor, a forward biased diode and an N-channel switching transistor series-connected between the high voltage and the ground. The gate of the N-channel transistor is controlled by a switching signal C in one arm and by the complementary switching signal C in the other arm. Such a structure enables the stress undergone by the load and switching transistors of the switching circuit to be reduced by several magnitudes.