Abstract: A one-pin integrated crystal oscillator in a Colpitts configuration employs a differential amplifier, provided with a feedback network, as an input gain stage. This achieves an enhanced stability and independence from temperature variation, a high Q figure, and a short start-up with a relatively small area of integration.

Abstract: A controlled gain transconductor (20) which comprises a transconductance stage (3) having at least two input terminals (I1, I2) and at least two output terminals (O1, O2), an active load (4) connected to the output terminals of the transconductance stage and a control circuit (5) for the active load (4) connected between said output terminals (O1, O2) and the active load (4).Also provided is a circuit portion (10) being a replica of the transconductance stage (3), the active load (4) and the control circuit (5). This replicated portion (10) has an output connected to the control circuit (5) of the transconductor (20) to provide a predetermined voltage value (Vc) required for adjusting the DC gain of the device.

Abstract: A supply-voltage-monitoring circuit, for low-power integrated circuits, in which charge-sharing through a switched-capacitor chain is used to couple the supply voltage to a dynamic sensing node. The dynamic sensing node drives a half-latch, which is stable in a no-alarm condition.

Abstract: A low power parking meter to control two or four parking bays. A display, either by a flag-wheel or a digital display will normally indicate the status of each bay. When funds are deposited without indicating the bay to be credited, the meter will escrow the amount until a bay is chosen. The meter normally operates in an idle loop unless an individual bay is being checked or vended.

Abstract: An auditing system for vending machines, preferably parking meters, that facilitates external exchange of digital information. The instant auditing system provides for electronic interrogation of the parking meter circuitry from portable, hand-held apparatus. The auditor is capable of processing and storing data derived from parking meters. In one form of the invention, communication is derived through the meter debit card payment slot. In an alternative embodiment data is optically exchanged and communicated between the auditor and the parking meter through infrared light. The auditor of the present invention can be interfaced with a personal computer through a standard RS232 serial port and appropriate interfacing software.

Abstract: A byte erasable memory with an EEPROM type functionality that can be integrated in a fully compatible way with a standard FLASH process is composed by a matrix of FLASH cells organized in n bytes, each of m bits, addressable through a plurality of wordlines and bitlines. The EEPROM-type memory has an auxiliary selection structure composed of an n number of byte select transistors, a plurality of individually selectable source biasing lines and a plurality of select lines in the same number of the wordlines and selectable in a biunivocal way with the wordlines. The cells of a byte have a common source that is accessed and individually selectable through the respective select transistor.

Abstract: In a demand-paged virtual memory system, the pages are arranged in the virtual memory space in groups. In order to translate an address from the virtual address space to a physical memory address space, the virtual group address component is input to a contents addressable memory (767), which outputs a group code (767), and the group code and virtual page address component (768X,Y) are input to a RAM page table (750) which outputs the page address. When the physical memory capacity is substantially smaller than the virtual address space, the CAM provides a large saving in page table size. In the case where the data-elements provide a plural-dimensional representation, for example as in pixel data, the pages include data elements which are contiguous in each of the plural dimensions in order to reduce the amount of page-swapping between the physical memory and a paging memory. The data-elements in the physical memory are accessible in parallel as contiguous patches.

Abstract: In a method for the testing of integrated circuits on wafers, the testing is facilitated by setting apart a test circuit zone on the wafer. The test circuit zone comprises contact pads to which it is possible to apply the tips of a tester, and also comprises a demultiplexer to transmit test stimuli to one out of N buses at the output of the demultiplexer. The output buses of the demultiplexer extend between the rows of chips on the wafer. Column selection conductors extend between the columns of chips. The demultiplexer and a decoder, both controlled directly by the tester, enable the selection of one chip at a time for testing. The testing tips are not shifted from one chip to the next one. The wafer is then sliced into individual chips.

Abstract: A data processing and memory system for transferring data elements page-by-page between several memories and modifying the data elements in the first memory. In order to reduce the set-up time when generating a new image, the processor stores the background color of the image for each new page. Then, when each new page is transferred to one of the memories, the background color is repeated for each data-element in the page.

Abstract: A circuit for the detection of current leaks on a bit line of a memory (such as an EPROM or flash EPROM), which includes a current generator and a means to apply zero volts to the gates of all the cells of the bit line. The detection information is delivered by a comparison circuit. It corresponds to the result of the comparison between the test current and the current flowing in the bit line. Advantageously, the detection circuit is incorporated into the read circuit of the memory. Also disclosed is the associated detection method and a memory circuit includes a detection circuit.

Abstract: A circuit to detect the crossing of at least one voltage threshold by an input voltage of an integrated circuit has two arms mounted in negative feedback configuration, each comprising a forward biased diode in series with a current generator. The current generator of an arm is controlled in voltage by the other arm. An inverter calibrated to detect a crossing of a given threshold is connected at input to the connection point between the diode and the generator of one of the arms.

Abstract: The use of an O--N--RTN (Oxide-Nitride-Rapid Thermal Nitrided Polysilicon) interpoly dielectric multilayer instead of a customary O--N--O (Oxide-Nitride-Oxide) multilayer in the floating gate structure of a progammable, read-only memory cell has beneficial effects on the performance of the cell and facilitates its scaling.

Abstract: The breakdown characteristics of a lateral transistor integrated in an epitaxial layer of a first type of conductivity grown on a substrate of an opposite type of conductivity and comprising a drain region formed in said epitaxial layer, are markedly improved without recurring to critical adjustments of physical parameters of the integrated structure by forming a buried region having the same type of conductivity of the substrate and a slightly higher level of doping at the interface between the epitaxial layer and the substrate in a zone laying beneath the drain region of the transistor.

Abstract: A circuit for limiting power dissipation through telephone subscriber line power supply interface devices, by using a pair of final stages to which an external component effective to dissipate power is connected. By use of separate discrete reference circuits, the presence of excessive common mode current is detected; and when this occurs, current to the driver stages is controlled at a lower magnitude.

Abstract: To provide efficient protection, in reading mode, of the stored data elements, the integrated circuit has an EEPROM type memory and a lock (L) protecting the zone of the memory. The memory contains a read-protected password (PW) and the circuit has means to release the lock (L) if the circuit receives a write command at the address of the password of the same encrypted password (PW). Application notably to electronic systems and instruments using confidential codes, such as car radios.

Abstract: A packaging structure is disclosed for a semiconductor device, having a body configured to include at least one part provided with some terminating rheophores and shaped to form a connector member for direct coupling to a standard connector member from an external circuit. A connector assembly is also disclosed which is fully sealed from moisture and comprises the packaging structure. The invention has an advantageous application in the field of electric systems for motor vehicles.

Abstract: A graphics processing system in which sub-pixel correction is implemented in a new and more economical way. A half-pixel offset is originally imposed on both the X and Y axes, so the sub-pixel correction value may be positive or negative. A relatively coarse resolution is used for subpixel correction, so that the DDAs (and other functional blocks) do not have to perform a full multiply: instead they merely perform simple add operations (addition of partial products) to derive the necessary offset from the delta-X values, using a proportionality constant provided by the rasterizer. The DDAs preferably include a "guard band" in their calculations, so that values which exceed the maximum (e.g. 255, for 8 bits of subpixel resolution) do not wrap to zero; instead the output is held at the maximum until the computed value comes down below the maximum.

Abstract: A high density, mixed technology integrated circuit comprises CMOS structures and bipolar lateral transistors, the electrical efficiency and Early voltage of which are maintained high by forming "well" regions through the collector area. The operation determines the formation of a "collector extension region" extending relatively deep within the epitaxial layer so as to intercept the emitter current and gather it to the collector, subtracting it from dispersion toward the substrate through the adjacent isolation junctions surrounding the region of the lateral bipolar transistor. Under comparable conditions, the ratio between IcIsubstrate is incremented from about 8 to about 300 and the Early voltage from about 20V to about 100V. The V.sub.CEO, BV.sub.CBO and BV.sub.CES voltages are also advantageously increased by the presence of said "well" region formed in the collector zone.

Abstract: A high conversion speed analog-to-digital converter is constituted by a plurality of comparison cells which in successive steps determine first the four most significant bits of the analog-to-digital conversion and then the least significant bits of the same, having first accomplished the reconversion of the four most significant bits to analog and their subsequent subtraction from the input signal.

Abstract: A crosspoint for a switching matrix constituted by enhanced P-channel and N-channel MOS transistors. Each input line conductor (Ii1 and Ii2) is connected to an input of a first differential amplifier (M3, M4), each leg of which is associated by a current mirror circuit to a first current source (M9, M10, M11) enabled by a selection input (Sij) of the crosspoint. The outputs of the first differential amplifier are connected to a second differential amplifier (M1, M2) fed by a second current source (I) common to all the crosspoints of a same column. The outputs of the second differential amplifier are connected to the pair of conductors (Oj1, Oj2) of an output column, an extremity of this column being connected to the high voltage source (Vdd) through a resistor (R).