Abstract: A source/sink current generating circuit is arranged to generate source and sink currents which are matched and insensitive to fan out. This is achieved by using a biasing transistor (Q13) between first and second current mirrors which generate respectively the source and sink currents.

Abstract: The disclosure relates to integrated circuits and, notably, to memories. A description is given of a bistable type of programmable, non-volatile memory, namely a memory that can take one state or another by the programming of one of two floating-gate transistors of the cell. To program a cell such as this, there are two transistors for the application of a programming voltage (VPRG). In order that the signals going through the programming paths (in particular the address signals) may not disturb the state of the cell in reading mode, provision is made for two isolation transistors interposed between the transistors for the application of the programming voltage and the drains of the floating-gate transistors. These isolation transistors are made conductive by a signal CAMSEL solely for a programming operation and solely for only one group of cells to be programmed. These cells can be applied notably to the storage of defective address elements in the redundancy circuits of large-capacity memories.

Abstract: A decision circuit receives input addresses of instructions to be executed and data addresses to which the instructions have to be applied. The decision circuit either allows the execution of the instruction or prohibits the execution of the instruction if the instruction leads to a false operation or to a fraudulent attempt to divulge the system contents. A buffer register stores the instruction addresses and subsequently presents them to the decision circuit simultaneously with the data addresses. This device applies particularly to the protection of electronic integrated circuit memory cards.

Abstract: A voltage multiplier for relatively high output current has its design output voltage stabilized and rendered independent of process spread, temperature, supply voltage and output current level, by a stabilization loop driving the switch that cyclically connects to ground a charge transfer capacitance of the functional voltage multiplier circuit. The feedback loop comprises an integrating stage, stabilized by creating a low-frequency zero in the transfer function for compensating one of two low-frequency poles of the transfer function of the whole circuit.

Abstract: A switching power supply in which the oscillation frequency is dynamically controlled to have an instantaneous frequency value which is reduced when the power line waveform is near its peaks. This is preferably accomplished by a divider circuit, which provides an output current proportional to the ratio between the instantaneous value of the rectified voltage and the long-term-averaged value of that voltage. This output current is fed into a ramp generator, to dynamically shift the frequency of the ramp generator as the output current changes. This circuit is indifferent to power line voltage and frequency (over a fairly wide range), and therefore may be used in different countries having different power standards.

Abstract: A high voltage semiconductor component having a low stray current comprises a central region (N.sup.-) surrounded by P-type layers (P.sub.1, P.sub.2) forming with the central region first and second junctions (J.sub.1, J.sub.2). The first and second junctions have an apparent perimeter on a same main surface of the component. A groove is formed between said apparent perimeters and is filled with a passivation glass (18). The surface of the glass is covered, above the perimeter of each junction, with a metallization (21, 22) contacting the layer of the second conductivity type corresponding to the junction.

Abstract: A driver circuit, for an electronic switch which is to be operated from a clock signal, comprises an inverter driven by the clock signal, and a voltage doubler which is connected to supply the inverter and connected to be driven by the complementary clock signal.

Abstract: In a device for the protection of integrated circuits against electrostatic discharges, the protection structure comprises a thyristor with an N+ region connected to the ground, a P- substrate, a deep N- well forming a gate region, and a P+ region connected to an external connection pad to be protected. The gate region is connected by a low-value resistor (with a maximum value of a few ohms) to the pad. This resistor increases the current for which the thyristor gets triggered and eliminates certain risks of the destruction of the circuit.

Abstract: A data-array processing system with a memory for storing an array of data-elements, a processor to perform a series of operations on data elements stored in a first section (832) of the memory and to copy data from the first section to a second section (830) of the memory after each series of operations, and output hardware, such a video processor and monitor, for outputting the data-elements in the second section. In order to reduce unnecessary copying of data-elements from the first section to the second section, the processor sets flags indicative of each of the of portions (e.g. P, Q, R, S) of the first section which is modified during that processing operation, and checks the flags during the subsequent copying operation to copy only the flagged portions.

Abstract: The turn-off delay time of a low-side driver (output power transistor), may be independently reduced and eventually made identical to the turn-on delay time by employing an auxiliary current generator that may be controlled by the same switching signal that controls a current generator employed for discharging the control node of the low-side driver, in order to provide an augmented discharging current during a first phase (only) of a turn-off process. The contribution to the capacitance discharge current provided by said third current generator is automatically interrupted by means responsive to the voltage present on the driving node of the low-side driver, when it approaches saturation.

Abstract: The contrasting requirements of low power consumption during operation and ability to function under drastic drops of the supply voltage at start-up of output power stages of an electric system of self-generation and recharge of a storage battery, are satisfied by an output power driving stage composed of a bipolar transistor and a field effect transistor, functionally connected in parallel to each other and having independent control terminals. A control signal is selectably switched either to the base of the bipolar output transistor or to the gate of the field effect output transistor, depending on the level of the supply voltage. A comparator comparing the voltage present on the supply node with a reference voltage controls a selection switch. The low threshold of the bipolar transistor ensures functioning at start-up, while the field effect transistor provides a low power consumption during normal running conditions.

Abstract: A circuit for the detection of current leaks on a bit line of a memory (such as an EPROM or flash EPROM), which essentially utilizes a current generator and a circuit to apply zero volts to the gates of all the cells of the bit line. The detection information is delivered by a comparison circuit. It corresponds to the result of the comparison between the test current and the current flowing in the bit line. Advantageously, the detection circuit is incorporated into the read circuit of the memory. Also disclosed is the associated detection method and a memory circuit using a detection circuit such as this.

Abstract: A data array processing system comprises a memory system for storing an array of data elements and addressable by a single address, a plural number N of processors (PROC(0)-(15)) capable of processing data elements in parallel, and an address bus. In order to allow parallel access to the memory system where possible, but permit the processors also to access different addresses, each processor is selectable to supply its respective required address (xq, yq) via the address bus to the memory system to access the memory, and each non-selected processor is operable to determine whether it requires access to the address (xq, yq) on the bus, and if so to access the memory system at the same time as the selected processor.

Abstract: To acquire measurement data elements during a tomography type experiment in nuclear medecine, with a gamma camera having two detector heads, each of these heads is oriented on a sighting center P while the set of two heads rotates about a center of rotation Ia of the apparatus, the center of rotation being offset from the sighting center. It is shown that this approach provides speedier operation for the acquisition and also contributes to the preparation of tomography images that are more precise and more easily computed.

Abstract: To connect an apparatus to a transmission channel, use is made of a device comprising a first coupling circuit to couple the device to the channel, a second circuit to process the signals received or transmitted and to verify that they conform to a pre-set standard, and a third circuit, normally a microprocessor, connected firstly to the processing circuit and secondly to the apparatus to make it carry out instructions corresponding to the information elements received. The second circuit comprises a control register associated with the type of the signals transmitted and a buffer memory to receive the signals transmitted or to be transmitted. The microprocessor is then made to carry out the instructions loaded into a program memory of this microprocessor as a function of the state of this control register.

Abstract: A circuit for regulating the charging time of the output node of an amplifier at start up. The output node commonly comprises an external soft-start capacitor charged by a current delivered by a pull-up transistor of a push-pull output stage of the amplifier, through a decoupling diode that is functionally connected between the output node of the amplifier and a terminal of the external soft-start capacitor. The present application provides a current mirror feed back circuit capable of mirroring the charge current of the external soft-start capacitor onto the driving node of the pull-up transistor of the output stage of the amplifier. The regulating circuit permits use of an external capacitance of extremely small size. Upon the reaching of a fully charged condition by the external capacitor, the control circuit self-isolates and does not influence in any way the normal operation of the amplifier.

Abstract: A power-on reset circuit which employs a supply voltage sensing branch for triggering a first inverter of a pair of cascaded inverters. The intrinsic static consumption of such a POR circuit is strongly reduced by employing a current generator, which is automatically forced to deliver a reduced current during the operation of the integrated circuit, for biasing two transistors functionally connected in said voltage sensing branch into a subthreshold operating condition.

Abstract: A decoded counter employing a shift register and a zero-detect circuit has the ability of returning to a correct state within a limited number of clock cycles if an invalid state is accidentally assumed by the counter. One of the flip-flops is provided with synchronous set while all the other flip-flops of the shift register are provided with synchronous reset. The output of the last flip-flop of the register drives a single set-reset line common to all the flip-flops and the pull-up line of the zero-detect circuit is connected to the input of the first flip-flop of the register. Optionally, one of the flip-flops may be provided with asynchronous set and the others with an asynchronous reset, for initializing the counter in a certain state through a single clear-load line.

Abstract: A padded cover for use with a mattress which provides added postural support (as well as extra thermal insulation and padding). The padded cover includes a sheet of support material which covers essentially the full length of the mattress. This sheet of support material is stiffened over the middle part of the mattress length. Thus, this arrangement provides extra firmness under the torso, while maintaining an essentially flat upper surface. This cover structure can be retrofitted to existing mattresses. The disclosed innovations also provide improved methods for manufacturing bedding material with stable and longitudinally nonuniform postural support. For example, in the presently preferred embodiment, three layers are fed into a standard quilting machine: an upper layer of ticking, a middle layer of convoluted-foam support material, and a bottom layer of quilt backing. The support material thus is quilted between the two other layers, giving a quilted fabric that may be made into a mattress cover.

Abstract: A voltage-current amplification circuit comprises two sub-circuits (B1, B2), each of which comprises a differential amplifier (D), a resistor (R4), a transistor (T), and a first switch (K1) connected between the transistor base and ground. Each sub-circuit (B1, B2) also comprises an additional amplifier (A1, A2), and an additional resistor (R2a, R2b), respectively. The inputs of the additional amplifiers being connected to ground through a common resistor (R) and to the emitters of the two transistors through a common resistor (R1). Each sub-circuit further comprises a second switch (K2) formed by a single transistor.