Abstract: A bipolar control transistor, forming part of an integrated current-limiter device comprises inside an epitaxial layer superimposed over a semiconductor substrate of a first type of conductivity, a base region of a second type of conductivity accessible from a base contact and regions of collector and emitter of the first type of conductivity contained in the base region and accessible from respective collector and emitter contacts. The base region comprises at least one highly-doped deep-body region which contains almost completely said emitter region, a lightly-doped body region which contains the collector region and an intermediate-doped region which co-operates with the first deep-body region to completely contain the emitter region and a surface area of the base region that is included between the regions of collector and emitter.

Abstract: A system for storing and processing an array of data-elements formatted as a plurality of pages of the data elements, and especially for use in a demand-paged dual memory system, comprises a memory in which each memory location has a capacity of, for example, 32 bits and a processing means for processing data elements and reading the data elements from and/or writing them to the memory. In order to enable full use to be made of the memory and to facilitate the use of demand-paging when dealing with data-elements having less bits, for example 16 or 8 bits, a plurality of such data-elements are stored at different bit levels in each memory location so that at no memory location is there stored data-elements from more than one page.

Abstract: A protection device, for a telephone (or other load) 27 in series with an external protection transistor 2, includes a sensor 6 for detecting common-mode current into the load. The output of the sensor 6 is connected to affect a current source/sink combination, and imbalance in this source/sink combination produces a voltage shift which is indirectly connected to control the protection transistor.

Abstract: A circuit for providing a reference current comprises first and second matched transistors, each of which has a control node and a controllable path and each of which is connected so that a current setting resistor is in the controllable path of the second matched transistor, the current setting resistor having a value, current set in the controllable path of the second matched transistor is related to a difference in voltage characteristics between the first and second matched transistors and to the value of the current setting resistor, and third and fourth matched transistors, each of the third and fourth matched transistors having a controllable path connected respectively to the controllable paths of the first and second matched transistors, and control electrodes of the third and fourth matched transistors connected together; a set of output transistors connected to the circuit to supply the reference current in dependence on a set current; and a fifth transistor having a controllable path between a bia

Abstract: In a memory circuit, the word line decoder includes a memorization logic circuit that provides for the memorizing of the selection of the word lines. This memorization provides for the simultaneous erasure of all the words lines for which the selection has been memorized.

Abstract: In an integrated circuit with protection against electrostatic discharges, there is provided a first voltage limiter connected between a pad to be protected and a ground bus. This first limiter is placed the peripheral part of the integrated circuit in the vicinity of the pad And there is provided a second voltage limiter directly connected to a circuit element to be protected. This second limiter is placed in the useful part of the integrated circuit and not in the peripheral part. Thus, the risks related to the resistors of the ground bus, crossed by high electrostatic discharge currents, are avoided.

Abstract: A power supply in which control of the switch-on instant of a power device of a boost-circuit (operating in a discontinuous mode) is implemented by monitoring the current which actually flows through the "fly-back" inductance. The current is monitored on a sensing resistance, and, by the use of a comparator, a signal is produced for enabling/disabling the transfer to an input of a PWM driving circuit of a switch-on signal produced by a null detector. This configuration provide good noise immunity, which is particularly useful in power-factor-correction applications, and reduced power dissipation.

Abstract: In an integrated circuit, a diode is interposed between the semiconductor substrate and the contact pad to an external bias voltage, and the substrate is biased at an internal voltage reference. Between each contact pad of the integrated circuit and semiconductor substrate, there is positioned a protection device against permanent overloads and a protection device against electrostatic discharges. By isolating the semiconductor substrate from the external voltages source and by placing a protection device between each contact pad and the substrate, a broad, general protection of the integrated circuit is obtained against all the destructive phenomena such as overloads, positive and negative overvoltages, polarity reversal and electrostatic discharges.

Abstract: A method for eliminating the bird's beak from selective oxidations of semiconductor electronic devices having a semiconductor substrate (1) which is covered by a pad oxide layer (2) covered, in turn, by a first layer (3) of nitride, and wherein at least one vertical-walled pit (11) is defined for growing an isolation region, comprises the sequential steps of: selectively etching the oxide layer (2) within the pit (11) to define peripheral recesses (6,8) between the substrate (1) and the nitride; filling the recesses (6,8) with nitride; and growing oxide in the pit (11) so as to form the isolation region contrasting the nitride portions (9,10) which occlude the recesses (6,8).

Abstract: Memories in integrated circuit form can have several amplifiers per data contact. To increase the possibilities of redundancy with a given number of redundancy columns without, causing too much space near the memory zone to be occupied by complicated multiplexers, the address AP used to select a single amplifier for each contact is used also to select one group of memories among several groups (as many groups as there are amplifiers per contact) in a defective address storage register. Only the defective addresses of this group are applied to a comparator used to detect whether a defective column address is received by the memory. A correlation is thus set up between the place where the defective column is located and the place where the redundancy column, which will be used to replace it, is located. This correlation results from the simultaneous selection by AP of a group of amplifiers and of a group of defective column addresses connected to these amplifiers.

Abstract: A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N- epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor.

Abstract: A current generator which includes a first bipolar transistor, the base of which is connected to a reference voltage and the emitter to ground through a first resistor. A first current mirror is connected to mirror the emitter current of this first transistor. The mirrored current is augmented by the base current of a second transistor (matched to the first transistor), and by current Vbe/R passed by a second resistor (matched to the first transistor), which is connected between the base and emitter of the second transistor. The current thus augmented drives a second current mirror. The output of the second mirror provides a precise reference current, determined by the reference voltage and the resistor magnitude.

Abstract: A transconductor stage for high-frequency filters operated on a low voltage supply, being of a type which comprises an input circuit portion having signal inputs, further comprises a pair of interconnected differential cells (2,3) being associated each with a corresponding signal input. Each cell incorporates at least one pair of bipolar transistors (Q1,Q2;Q3,Q4) having at least one corresponding terminal thereof (e.g. the emitter terminal) connected in common.

Abstract: The amplifier includes a pair of bipolar input transistors (Q1, Q2), each having a base adapted to receive a differential input signal, a collector and an emitter which is biased by a first fixed current source (M7, M8) of its own and a degeneration resistor (R) which connects the emitters of the two bipolar transistors. The collector of each bipolar transistor is also biased by a second fixed current source (M5, M6) with a smaller current than that of the first source, and the collectors of the two bipolar transistors are furthermore connected to the input terminals of respective MOS amplifier devices (M1, M2, M3, M4, R.sub.L). The amplifier can be made in BCD, BiCMOS or purely CMOS technology, in which case the bipolar transistors are obtained as lateral bipolar transistors.

Abstract: A stage of both input and output configurable for operation with low and high voltages, comprises:first (M1), second (M2) and third (M3) transistors, each having first and second terminals and a control terminal, the first and second terminals and control terminal of the first transistor (M1) being respectively connected to a first terminal of a voltage supply, the first terminal of the second transistor (M2), and a drive circuit means, the second terminal and control terminal of the second transistor (M2) being respectively connected to a circuit node (A), forming an input/output terminal of the stage (1), and to the drive circuit means, the first and second terminals and control terminal of the third transistor (M3) being respectively connected to a second terminal of the voltage supply, the circuit node (A), and the drive circuit means;at least one diode (D2) connected between the first and the second terminal of the second transistor (M2); andan input circuit (3) having a first input terminal connected to

Abstract: A manufacturing process for an integrated circuit which includes at least one vertical-current-flow MOS transistor. The patterned photoresist which screens the body implant is also used to mask the etching of a nitride layer over a pad oxide. After the photoresist is cleared, the nitride pattern is transferred into the oxide, and the resulting oxide/nitride stack is used to mask the source implant. The nitride/oxide stack is then removed, the gate oxide is grown, and the gate layer is then deposited.

Abstract: A circuit for protecting nonvolatile memories against loss of Vcc while Vpp is high. An NMOS gated by Vcc is connected, in series with a load element, between Vpp and ground. The node between the NMOS and the load element gates a PMOS which is interposed between Vpp and the memory. Thus when Vcc fails while Vpp is high, the NMOS will turn off, and the load element will pull up the gate of the PMOS to turn it off, interrupting the Vpp supply. This prevents spurious write or erase operations under these circumstances. The circuit can be designed to trigger at threshold voltages as low as V.sub.TN, and is thus particularly advantageous for operation with specified Vcc values of 3 Volts or less.

Abstract: A circuit for the generation of a time-stabilized output pulse Iout comprises a capacitor biased by two completely independent voltages whose bias voltages are fixed by a current generator through current mirrors and are therefore very stable.

Abstract: In a half-bridge output stage employing a complementary pair of output power transistors, each driven through an integrating stage for controlling the slew-rate, a single integration capacitance is conveniently shared by the two integrating stages that drive the power transistors. A pair of switches connect the single integrating capacitance to the input of either one of the two integrating stages and are controlled by a pair of nonoverlapping signals that have a certain advance with respect to the pair of logic signals that drive the half-bridge stage. In the case of a driving system of a multi-phase machine, the two configuring switches of the single integration capacitor may be driven by a pair of control signals that drive a different phase winding of the multi-phase machine, thus eliminating the need for dedicated circuitry for generating said pair of anticipated signals to control the configuration switches.

Abstract: A device for doubling or dividing by 2 the flow rate of series bits comprising a succession of first one-bit registers (R4-R0) actuated at a frequency F; a second register (R) actuated at a frequency 2F; an input terminal (IN) connected to the input of the first (R4) of the first registers and, through a first gate (T5), to an internal line (L) connected to the input of the second register; first multiplexers (M4-M1) connected to the input of each second (R3) to last (R0) of the first registers for selecting either the output of the preceding register, or the internal line, or still the output of the second register; a second multiplexer (M), which selects either the output of the last (R0) of the first registers, or the output of the second register, or filling bits; second transfer gates (T4-T0) between the output of each first register and the internal line; and means for controlling the various gates and multiplexers.