Abstract: An Ethernet switch includes 12-Volt and 48-Volt power sourcing modules, system software, Ethernet interface modules and optional power over Ethernet (PoE) modules. The Ethernet interface modules are motherboards that include the circuitry required to implement a non-PoE system. The PoE modules are daughter boards that include the circuitry required to supply powered devices in a PoE subsystem. A PoE module may be connected to a corresponding Ethernet interface module. During start up, all of the Ethernet interface modules are first powered up in response to the 12-Volt power sourcing module. If the system software subsequently determines that the 48-Volt power sourcing module is operational, then (and only then) the system software attempts to detect the presence of any PoE modules. Upon detecting one or more PoE modules, the PoE modules are initialized and configured, thereby enabling PoE operation.

Abstract: A method of generating a quadrature local oscillator (LO) frequencies is provided. In this method, a voltage-controlled oscillator (VCO) frequency can be mixed with a divided version of the VCO frequency to generate mixed signals. A lower sideband of the mixed signals can be selected for the quadrature LO frequencies to minimize the occurrence of spurs. Notably, the divided version is 1/N of the VCO frequency and the VCO frequency is a radio frequency (RF) channel frequency times a ratio N/(N?1).

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A memory module assembly includes a heat-sink plate attached to one or more of the integrated circuits (e.g., memory devices) of a memory module PCBA by adhesive. The heat-sink plate includes an elongated base structure, a first contact plate extending away from the base structure such that a step-like positioning surface is defined therebetween, and heat-exchange fins extending from the opposite side of the base structure. An optional upper heat-sink plate is secured to a second side of the PCBA by a second adhesive layer, and contacts the lower heat-sink plate to facilitate heat transfer to the heat-exchange fins. The adhesive is either heat-activated or heat-cured. The adhesive is applied to either the memory devices or the heat-sink plates, and then compressed between the heat-sink plates and memory module using a fixture. The fixture is then passed through an oven to activate/cure the adhesive.

Abstract: An amplifier with linearization feedback includes an amplification stage that receives a feedback control signal from an envelope detection feedback network. The envelope detection feedback network controls the gain of the amplification stage based on an envelope of an input signal of the amplification stage, an envelope of an attenuated version of an amplified output signal of the amplification stage, and an offset adjustment signal generated by an offset calibration block. The envelope detection feedback network can include single stage or multiple stage envelope detectors. The amplification stage can include multiple, serially connected amplifiers. The gain of at least one amplifier in the amplification stage may be controlled by the feedback control signal. Additionally, the gain of some of the amplifiers in the amplification stage may be controlled digitally by gain adjustment signals based on comparing the feedback control signal to one or more reference signals.

Abstract: An RF coupling circuit including a transformer and a parallel AC-coupling capacitor can advantageously ameliorate substantial attenuation of a signal, prevent destabilization of any feedback loop, and simplify the circuit design process. The AC-coupling capacitor can act as an “averager”, i.e. both the input and output sides of coupling circuit represent capacitances equal to the average of the input and the output capacitances. Thus, the inductors for tuning them out can become equal, thereby allowing a symmetric (or near symmetric) transformer to be used in the RF coupling circuit. When tuned properly, the transformer plus AC-coupling capacitor can also advantageously provide better in-band gain as well as frequency selectivity than other conventional coupling circuits.

Abstract: A system and method are described for repeatedly and efficiently performing a wireless communication channel survey to determine whether comparable communications devices exist, which frequencies are in use, and the identities of the comparable communications devices. A beacon data table stores received beacon data which is used to predict beacon arrival times, thereby allowing a receiver to be tuned away from an active data communications channel for a shorter dwell time than a beacon period. A further efficiency can be gained if beacon generators cooperatively stagger their beacon times according to one or more measurable characteristics of the beacon generator, e.g. the operating channel number and the SSID.

Abstract: A voltage buffer with current reuse is described. This voltage buffer can advantageously provide a relatively wide voltage differential using a relatively low current. In one embodiment, a slave branch can be used to minimize potential spikes/glitches in the voltage buffer.

Abstract: A device for extruding/dispensing materials on a substrate includes a housing with at least two channels formed to facilitate flow. The housing includes entrance ports for each of the channels for receiving different materials. The housing further includes an exit port for co-extruding the materials on the substrate to generate a relatively fine feature with a relatively high aspect ratio.

Abstract: An accurate total error rate performance can be measured using a computed error vector magnitude (EVM) per stream. Using this EVM, the receiver or the transmitter can advantageously generate an optimized modulation and coding scheme (MCS) that corresponds to a specific number of streams, modulation and coding rate for the transmitter. For example, the receiver can compute an SNR from the EVM and then use an SNR vs. MCS table to determine the optimized MCS. In contrast, the transmitter can receive an EVM-to-RSSI mapping and an EVM-to-MCS mapping from the receiver. These mappings and an EVM can facilitate selecting the optimized MCS.

Abstract: In a near-field heterodyne spectroscopy system, a near-field generation device receives the output of a pump beam source and is also made to vibrate or move at a frequency f to generate a modulated near-field beam having a near-field component. The outputs of the pump beam source and a probe beam source (optional) as well as the modulated near-field beam are directed to the same point on a sample. At least one of the outputs of the pump beam source and probe beam source is modulated at a frequency ?. Thus, the reflected beam that results from the interaction with the region illuminated by the modulated near-field beam is modulated at frequencies ?+f and ??f. Because the excitation is near-field, the electric field in the sample is evanescent and ensures a shallow probing depth as well as smaller lateral dimensions beyond diffraction limit.

Abstract: A current limited voltage supply including a transistor and a capacitor is provided for powering digital logic cells of an integrated circuit. The transistor is connected in a current mirror configuration, such that a constant reference current is mirrored through the transistor to create a first supply current. The transistor is coupled to the digital logic cells and the capacitor. The first supply current is used to charge the capacitor while the digital logic cells are not switching. While the digital logic cells are switching, the capacitor discharges to the digital logic cells, thereby providing the digital logic cells with sufficient energy to implement high-speed switching. The capacitor minimizes voltage fluctuations within in the current limited voltage supply, such that analog circuitry can be reliably powered from a different branch of the same current mirror circuit.

Abstract: A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a patterned polysilicon structure is formed over the dielectric layer. The patterned polysilicon structure includes one or more narrow polysilicon lines, each having a width less than the minimum gate width. The LDD implants for low and high voltage transistors of the same conductivity type are allowed to enter the substrate, using the patterned polysilicon structure as a mask. A thermal drive-in cycle results in a continuous diffusion region that merges under the narrow polysilicon lines. Contacts formed adjacent to the narrow polysilicon lines and a metal-1 trace connected to the contacts may increase the resulting capacitance.

Abstract: Background scanning can include using a power save mode to momentarily suspend transmission between a current access point and a client. Information regarding other access points can then be collected. The client can return to the current access point before communication between the client and the current access point is disrupted.

Abstract: A capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed, grooves are etched through the pre-metal dielectric layer to expose polysilicon structures, which may be salicided or non-salicided. A dielectric layer is formed over the exposed polysilicon structures. A conventional contact process module is then used to form contact openings through the pre-metal dielectric layer. The mask used to form the contact openings is then removed, and conventional contact metal deposition steps are performed, thereby simultaneously filling the contact openings and the grooves with the contact (electrode) metal stack. A planarization step removes the upper portion of the metal stack, thereby leaving metal contacts in the contact openings, and metal electrodes in the grooves. The metal electrodes may form, for example, transistor gates, EEPROM control gates or capacitor plates.

Abstract: Fluidic conduits, which can be used in microarraying systems, dip pen nanolithography systems, fluidic circuits, and microfluidic systems, are disclosed that use channel spring probes that include at least one capillary channel. Formed from spring beams (e.g., stressy metal beams) that curve away from the substrate when released, channels can either be integrated into the spring beams or formed on the spring beams. Capillary forces produced by the narrow channels allow liquid to be gathered, held, and dispensed by the channel spring probes. Because the channel spring beams can be produced using conventional semiconductor processes, significant design flexibility and cost efficiencies can be achieved.

Abstract: A concrete lid for an in-ground utilities box includes a plastic reinforcement structure filled with concrete. The plastic reinforcement structure includes one or more plastic sidewalls that protect the edges of the lid from damage. The upper and lower surfaces of the lid are exposed concrete (with the exception of the upper and lower edges of the one or more plastic sidewalls). The one or more plastic sidewalls laterally surround a plastic reinforcement grid, which is centrally located between the upper and lower edges of the one or more plastic sidewalls. The one or more plastic sidewalls can be integrally formed with the plastic reinforcement grid. The plastic reinforcement grid reinforces the concrete lid, eliminating the need for separate reinforcement material. Support struts can be used to support the plastic reinforcement grid while wet concrete is being poured into the plastic reinforcing structure.

Abstract: An improved method of forming a LED with a roughened surface is described. Traditional methods of roughening a LED surface utilizes strong etchants that require sealing or protecting exposed areas of the LED. The described method uses a focused laser to separate the LED from the substrate, and a second laser to roughen the LED surface thereby avoiding the use of strong etchants. A mild etchant may be used on the laser roughened LED surface to remove unwanted metals.

Abstract: A CMOS image sensor includes a pinned photodiode and a transfer gate that are formed using a thick mask that is self-aligned to at least one edge of the polysilicon gate structure to facilitate both the formation of a deep implant and to provide proper alignment between the photodiode implant and the gate. In one embodiment a drain side implant is formed concurrently with the deep n-type implant of the photodiode. After the deep implant, the mask is removed and a shallow p+ implant is formed to complete the photodiode. In another embodiment, the polysilicon is etched to define only a drain side edge, a shallow drain side implant is performed, and then a thick mask is provided and used to complete the gate structure, and is retained during the subsequent high energy implant. Alternatively, the high energy implant is performed prior to the shallow drain side implant.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.