Abstract: A method for heating or cooling a semiconductor wafer in semiconductor processing apparatus is described which comprises directing into contact with a surface of the wafer at least a portion of one or more components of the process gas to transfer heat between the wafer and a wafer support positioned in the apparatus adjacent to the wafer. Method and apparatus are also described for controlling the total flow of process gas through the apparatus and for monitoring the pressure in said apparatus to maintain the desired pressure therein.

Abstract: Magnetic confinement of electrons in a plasma reactor is effected using electro-magnetic coils and other magnets which generate respective magnetic fields which are mutually opposed and substantially orthogonal on their common axis to the major plane of a wafer being processed, instead of being aligned and parallel to the major plane as in prior magnetically enhanced plasma reactors. The respective magnetic fields combine to yield a net magnetic field which is nearly parallel to the wafer away from the magnetic axis so that electrons are confined in the usual manner. In addition, a magnetic mirror provides confinement near the magnetic axis. The E.times.B cross product defines a circumferential drift velocity urging electrons about a closed path about the magnetic axis.

Abstract: A semiconductor wafer is provided with magnetic material about the periphery for magnetically clamping the wafer on a seating gasket at the processing station. The seating gasket is annular for peripherally supporting the wafer. An electro-magnet establishes a peripheral station magnetic field which attracts the wafer magnetic material to form the clamp. The station magnetic field may by reversed to levitate the wafer onto and off of the seating gasket.

Abstract: A wafer processing system includes an autoloader mounted within a load lock for providing batch, cassette-to-cassette automatic wafer transfer between the semiconductor processing chamber and cassette load and unload positions within the load lock. The system provides rapid, contamination-free loading and unloading of semiconductor wafers.

Abstract: An inner lid is attached to a vacuum chamber, covering an inner region of the vacuum chamber. An outer lid, also attached to the vacuum chamber, covers the inner lid, leaving a region between the inner lid and the outer lid. A gas conduit allows gas to flow between the inner region of the vacuum chamber and the region between the inner lid and the outer lid. A filter is placed in or immediately outside the gas conduit to prevent particles from entering the inner region of the vacuum chamber from the region between the inner lid and the outer lid. Since the pressure is the same on the top and bottom of the inner lid, the inner lid does not flex and thus does not rub against the vacuum chamber when the vacuum chamber is pumped down or vented up.

Abstract: An improvement which allows precise positioning of wafers within cassettes in preparation for removal of the wafers by automated equipment. The improvement includes mounting two sawtooth jigs upon the surface upon which the cassette tray is to be placed which extend up into the cassette. Wafers within the cassette rest within the precisely aligned grooves of the sawtooth jigs.When the cassette is placed upon the surface, automated equipment can readily remove the precisely aligned wafers from the cassette.

Abstract: A magnetic field enhanced single wafer plasma etch reactor is disclosed. The features of the reactor include an electrically-controlled stepped magnetic field for providing high rate uniform etching at high pressures; temperature controlled reactor surfaces including heated anode surfaces (walls and gas manifold) and a cooled wafer supporting cathode; and a unitary wafer exchange mechanism comprising wafer lift pins which extend through the pedestal and a wafer clamp ring. The lift pins and clamp ring are moved vertically by a one-axis lift mechanism to accept the wafer from a cooperating external robot blade, clamp the wafer to the pedestal and return the wafer to the blade. The electrode cooling combines water cooling for the body of the electrode and a thermal conductivity-enhancing gas parallel-bowed interface between the wafer and electrode for keeping the wafer surface cooled despite the high power densities applied to the electrode.

Abstract: In a method for preparing a shield for use in a physical vapor deposition process, the shield is sputter-etch cleaned to increase adhesion of deposits in the physical vapor deposition process. The sputter-etch cleaning serves to loosen contamination which may for a diffusion barrier and prevent the deposits from bonding to the shield. Also, the sputter-etch cleaning creates a high degree of micro-roughness. The roughness allows for an increase in nucleation sites which minimize the formation of interface voids. In addition to sputter-etch cleaning the shield may be bead blasted. The bead blasting makes the surface of the shield irregular. This enhances interface cracking of deposited material on a microscopic scale, resulting in less flaking.

Abstract: A thermal reactor system for semiconductor processing incorporates a reaction vessel with a rectangular quartz tube with reinforcing parallel quartz gussets. The gussets enable sub-ambient pressure processing, while the rectangular tube maximizes reactant gas flow uniformity over a wafer being processed. The gussets facilitate effective cooling, while minimally impairing heating of the wafer by allowing minimal wall thickness. The thermal reactor system further includes a gas source for supplying reactant gas and an exhaust handling system for removing spent gases from and establishing a reduced pressure within the reaction vessel. An array of infrared lamps is used to radiate energy through the quartz tube; the lamps are arranged in a staggered relation relative to the quartz gussets to minimize shadowing. In addition, other non-cylindrical gusseted vessel geometries are disclosed which provide for improved sub-ambient pressure thermal processing of semiconductor wafers.

Abstract: An improvement which allows precise positioning of wafers within cassettes in preparation for removal of the wafers by automated equipment. The improvement includes mounting two sawtooth jigs upon the surface upon which the cassette tray is to be placed which extend up into the cassette. Wafers within the cassette rest within the precisely aligned grooves of the sawtooth jigs.

Abstract: A brassiere accessory comprises two elongated bands that can be fastened together at one end and is threaded through a grip means at the other end, said grip means having two slot openings for passage therethrough of a shoulder strap of a brassiere, and serrated edges opposite said slot openings for gripping said shoulder straps, and an arcuate opening through which an elongated band is threaded. The elongated bands can be fitted with length adjusting means.

Abstract: An ion implantation system is modified to allow variation in the size of the aperture of the mass resolving system, thereby allowing more ions of one mass or ion of more than one mass, such as isotopes, to pass through said opening. Including all isotopes of the desired dopant ions to be collected increases beam current, and consequently the throughput of the implantation process, reduces contamination, and improves the dosage control.

Abstract: A susceptor carrying semiconductor wafers for processing is suspended from a compliant attachment at its upper end and is lowered into a reaction chamber for processing. At the completion of processing, the susceptor is withdrawn vertically to permit a robot to unload the processed wafers and load unprocessed wafers. In order to fix the position of the susceptor during the loading operations, a support carriage is moved into position to engage the lower end of the susceptor. Noxious and corrosive chloride vapors are simultaneously withdrawn from the reaction chamber by a vacuum line attached to the support carriage.

Abstract: The temperature of a semiconductor wafer during annealing of metallization is accurately and indirectly monitored by supporting the wafer on a thin susceptor of constant emissivity and monitoring the temperature of the susceptor. The system has the added advantage of providing efficient, controlled heating of the wafer by radiant heating of the backside of the susceptor.

Abstract: An apparatus for feeding headed pins includes a frame having thereon a hopper into which the pins are placed. A ramp extends substantially horizontally from the hopper and has a plurality of spaced, parallel slots therein which are adapted to receive the pins with the heads of the pins seated on the surface of the ramp. At the end of the ramp is a transfer shuttle assembly which is adapted to feed pins from the slots into passages in a chute which extends vertically downwardly from the end of the ramp. The upper ends of the passages are offset from the ends of the slots. The shuttle transfer means includes a shuttle plate movable back and forth across the end of the ramp by means of pneumatic cylinders, and a plurality of gates mounted on the shuttle plate. Each gate has a notch in its end which can receive a pin.

Abstract: A semiconductor device, such as a MOSFET or IGT, with a deep base region having a high dopant concentration at least as high as 5.times.10.sup.19 atoms per cubic centimeter and a method of fabrication are disclosed. The novel method involves formation of the deep base region at a later stage in the fabrication and reduces the leaching of dopant from the deep base region, as well as achieving greater control over the dopant concentration in the deep base region. Further, the increased dopant concentration in the deep base region lowers the base shunt resistance of the device to provide improved electrical ruggedness. For IGTs, parasitic thyristor action is reduced.

Abstract: For fine line lithography of a reflective substrate, a layer of titanium nitride is applied between the reflective surface and the photoresist that is absorbant at the wavelength of light used to expose the photoresist. The resolution of the photoresist is improved, even when an absorbant dye is used in the photoresist. The titanium nitride can be readily removed at the same time as the reflective layer is patterned, thereby avoiding the need of a separate step to remove the absober layer during etching of the reflective substrate.

Abstract: A process for fabricating a power IC structure which includes the following masking steps:1. CMOS P well mask2. JFET (short-channel implant) mask3. Field oxide growth mask4. Deep P+ mask5. Polysilicon mask6. DMOS P well mask7. n-/n+ mask8. Contact window mask9. Metalization mask10. Overglass mask.

Abstract: An arc gap for an integrated circuit on a surface of a substrate of semiconductor material includes a first conductive strip over and insulated from the substrate surface. A layer of an insulating material is over the first conductive strip and a second conductive strip is on the insulating layer. The insulating layer has an opening therethrough which exposes at least a portion of the first conductive strip. The second conductive strip extends to substantially the edge of the opening in the insulating layer so that the two conductive strips are exposed to each other through the opening. The two conductive strips may be portions of a metallization pattern for the integrated circuit.

Abstract: The present invention sets forth an integrated circuit (IC) device wherein the IC chip includes peripheral circuits, such as input/output circuits, which are arranged non-perpendicular with respect to the rectangular shape of the active area of the IC. This structure permits positioning some of the terminal bond pads closely adjacent the corners of the chip without overlap of adjacent circuits.