Abstract: A circuit for limiting the load current through a transistor switch, where the load is connected between the collector of the transistor switch and a first power terminal and a resistive element, whose impedance is much less than that of the load, is connected between the emitter of the transistor switch and a second power terminal. The circuit includes first and second comparator transistors, with the emitter of the first transistor being connected to the emitter of the transistor switch and the emitter of the second transistor being connected to the second power terminal. The same potential is applied to the bases of the first and second comparator transistors whereby the difference between their base-to-emitter voltages is equal to the voltage drop across the resistive element. The collector currents of the first and second transistors are compared and the difference in the currents is used to control the conductivity of the transistor switch.

Abstract: Signals applied to the gate of an enhancement-mode field effect transistor by resistive coupling, via a dc-blocking capacitor, are self-biased. The self biasing is carried out by detecting the signal amplitude and applying a portion of the direct voltage from this detection to the gate of the field effect transistor through the coupling resistor.

Abstract: A circuit whose output is asymmetrical whereby the circuit makes a transition from a first state to a second state more slowly than from the second state to the first state a preset towards the second state prior to the application of data input signals to the circuit.

Abstract: In accordance with the present invention a method for forming an insulating layer over a substrate surface comprises providing first and second raised portions extending from the substrate surface, the first and second portions extending distances X.sub.1 and X.sub.2 respectively, and X.sub.2 being greater than X.sub.1. An insulating layer of thickness T.sub.3 is deposited over the surface so as to conform to the topography of the substrate surface and raised portions and a flowable layer is then deposited over the insulating layer. The flowable layer is next flowed so as to yield a substantially planar surface and then thinned until that portion of the insulating layer that overlies the second portion is exposed. The flowable layer and the exposed surface of the insulating layer are then simultaneously thinned so as to remove a greater thickness of flowable layer than insulating layer. The thinning is stopped when that portion of the insulating layer that overlies the first portion is exposed.

Abstract: A MOS/SOI field-effect transistor is made by applying a layer of a photoresist over the surface of a single-crystalline silicon layer which is on a substrate of an insulating material, such as sapphire. The surface of the silicon layer is along a (100) crystallographic plane. The photoresist layer is defined to provide an area of the photoresist layer over the area of the silicon layer where the transistor is to be formed with the edges of the photoresist area being along the edges of (100) crystallographic planes which are perpendicular to the surface of the silicon layer. The portion of the silicon layer around the photoresist layer is etched with an anisotropic plasma etch which etches the silicon layer along the (100) crystallographic planes which are perpendicular to the surface of the silicon layer to form an island of the silicon.

Abstract: A photodetector including a light transmissive electrically conducting layer having a textured surface with a semiconductor body thereon. This layer traps incident light thereby enhancing the absorption of light by the semiconductor body. A photodetector comprising a textured light transmissive electrically conducting layer of SnO.sub.2 and a body of hydrogenated amorphous silicon has a conversion efficiency about fifty percent greater than that of comparative cells. The invention also includes a method of fabricating the photodetector of the invention.

Abstract: A display comprises means for changing the polarization of light, such as a liquid crystal cell, and has a means for analyzing light on one side thereof. A means for diffusing light is disposed between the cell and the analyzing means. This arrangement results in a higher contrast ratio for the display than for the prior art arrangement having the analyzing means disposed between the cell and the diffusing means.

Abstract: An imaging array of the charge transfer type having improved sensitivity is disclosed. The array includes a plurality of substantially parallel charge transfer channels with channel stops therebetween which extend a distance into a semiconductor body. At least some of the channel stops have blooming drains therein for the removal of excess photogenerated charge. The improvement comprises potential barrier means which constrain electrical charge generated by absorption of light in the body to flow into the channels while preventing the loss of such charge by direct flow to the blooming drains. Potential barrier means include buried barrier regions extending a further distance into the body from those channel stops having blooming drain regions therein.The invention also includes an improved method of forming this array wherein the improvement comprises forming buried barrier regions containing a greater concentration of conductivity modifiers than the channel stops after the blooming drains are formed.

Abstract: There is disclosed herein a method of making a device made up of at least two separate parts each of which is formed of a patterned array with the parts being mounted one on the other, with the patterned arrays of the parts being aligned, such as a CCD imager having a color filter thereon. The two parts are made on separate substrates with a first alignment key being formed on each substrate. The first alignment keys are formed by photolithography using the same mask to form the first alignment keys on each substrate. The various features of each of the parts are then formed on each substrate with each feature being formed by a photolithographic step using a mask which is aligned to a first alignment key so as to align all the features. A second alignment key is formed on each substrate and is positioned on each substrate in the same relationship with a first alignment key.

Abstract: A method for forming a layer of silicon dioxide over a silicon island on an insulating surface wherein the layer on top of the island is thinner than on the sidewalls is disclosed. The silicon island is oxidized and a silicon layer is deposited thereover. A layer of planarizing material is deposited over the silicon layer. The planarizing layer is anisotropically etched until the surface of the silicon layer overlying the island is exposed. The silicon layer is in turn etched until the surface of the oxide layer overlying the island is exposed. The remaining planarizing material is removed and the remaining silicon layer is oxidized. The thickness of the gate oxide layer on top of the island may be controlled by again exposing the island surface and reoxidizing to a predetermined thickness. A conductive polycrystalline silicon electrode is deposited on the oxide-covered island. The disclosed method is particularly useful in the formation of MOSFETs.

Abstract: A voltage offset introduced in a differential amplifier stage by the addition of an offset current is rendered relatively constant by making the offset current a function of, and responsive to, the level of the differential input voltage applied to the differential amplifier stage.

Abstract: The present invention relates to a frame transfer charge-coupled device imager which includes along a major surface of a substrate of semiconductor material a photosensing array A-register, a temporary storage B-register and an output C-register. The C-register includes a channel region in the substrate and extending along the substrate surface across the ends of and substantially perpendicular to spaced, parallel channel regions of the B-register. The C-register also includes a plurality of parallel, conductive gates extending transversely across the C-register channel region substantially parallel to the B-register channel regions. The gates include a plurality of sets with a plurality of gates per set. One gate of each set extends to a conductive termination which extends along one side of the C-register channel region over the B-register and the gates of the other sets extend to conductive terminations which are along the side of the C-register channel region opposite the B-register.

Abstract: A hydrogen-oxygen fuel cell is provided which includes as the fuel a mixture comprised of about 40 to 60% by volume of formaldehyde and about 60 to 40% by volume of propionaldehyde. The operation of hydrogen-oxygen fuel cells is improved with regard to the amount of electrical power produced, the length of time of operation between discharges of the hydrogen-oxygen fuel cell and the number of times the hydrogen-oxygen fuel cell can be rejuvenated before replacement of electrolyte.

Abstract: A three part edge seal for an integrated circuit semiconductor chip is disclosed. The edge seal includes two separate layers of metal one of which overlays the other in electrical contact. One of the metal layers is in ohmic contact with a highly doped region formed in the planar surface of the semiconductor body. The two metal layers serve as an electrical conductor to distribute power to various portions of the integrated circuit contained in the chip and electrically charge the highly doped region to prevent migration of ions into the active areas of the integrated circuits.

Abstract: The yield of field transfer CCD imagers made in a wafer of single crystalline silicon is improved by making the imagers in groups of at least two imagers, and preferably four imagers, with the A-registers of all the imagers in a group being adjacent each other. The groups of imagers are formed in columns on the surface of the wafer with one group being at the center of the wafer and the other group being around the center group and positioned radially outwardly form the center group toward the edge of the wafer.

Abstract: A zener diode structure for integrated circuits is disclosed. The device includes a pair of opposing zener diodes separated by a parasitic resistance. The zener breakdown junctions of the two diodes are well below the surface of the device thereby reducing any adverse effect of stray surface charges and ultraviolet radiation. Further, the doping levels of the opposing diodes are selected to reduce drift in the breakdown voltage due to variations in operating temperature of the device.

Abstract: A method of producing a high frequency III-V FET and the resultant structure is described wherein a doped layer is formed on a wafer of undoped, semi-insulating III-V material. The structure is then etched to form a mesa after which, a channel region is regrown from an exposed portion of the III-V substrate. The formation of the channel region defines the source and drain regions. Ohmic contacts are then made to the source and drain regions after which a Schottky contact is made to the channel region.

Abstract: A high power thick film resistor having improved power handling capability is obtained with a resistor having two overlying thick film layers wherein the first thick film layer has a relatively low resistivity and the second thick film layer has a relatively high resistivity.

Abstract: A vertical MOSFET in a silicon wafer having opposing major surfaces includes a source electrode on one surface, a drain electrode on the second surface, and an internally disposed insulated gate. The silicon between the insulated gate and each of the major surfaces is of first conductivity type and the silicon that is laterally adjacent to the insulated gate is of second conductivity type, such that a predetermined voltage on the insulated gate creates an inversion channel extending a predetermined distance into the laterally adjacent silicon. That portion of the laterally adjacent silicon where the inversion channel is formed is of relatively lightly doped material, whereas other areas of the laterally adjacent silicon is relatively heavily doped.

Abstract: The semiconductor device includes a layer of silicon nitride (Si.sub.3 N.sub.4) beneath a phosphosilicate glass (PSG) layer. A silicon nitride impervious layer prevents the oxidation of underlying, exposed silicon regions during a "flow" step and any "reflow" step. Accordingly, the flow of the PSG layer can be conducted in an atmosphere containing steam, which means that the PSG layer can contain less than about 7% phosphorus by weight. The reduction of the phosphorus content of the PSG layer provides increased reliability for the semiconductor device. The method of manufacturing such a device is also disclosed.