Abstract: A novel integration scheme for forming power MOSFET, particularly forming salicided layers for both gate contact regions and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicided layers.

Abstract: The present invention discloses a projection apparatus comprising: a light source for emitting illumination light; a mirror device comprising a plurality of mirrors for generating an image by reflecting the illumination light toward a projecting direction by means of a deflecting operation; and a projection optical system which is placed in the optical axis of reflection light in the projecting direction of the illumination light incident to the mirror device and which projects the reflection light, wherein the optical axis of the illumination light incident to the mirror device and the optical axis of the reflection light in the projecting direction forms an angle that is larger than the expansion angle ? of the flux of the illumination light that satisfies NA=n*sin ?, where NA is the numerical aperture of the flux of the illumination light, and n is the reflectance.

Abstract: A projection apparatus implemented with a mirror device that includes a first electrode and a second electrode with an elastic hinge disposed between the first electrode part and second electrode. The elastic hinge supports a mirror and the mirror is controlled to deflect when drawn by a Coulomb force generated between the mirror and electrodes by applying a voltage to the electrodes. The projection apparatus further includes a light source for projecting a light to the mirror for modulating the light by deflecting the mirror to different deflection states. The light source suppresses the emission of the illumination light during a period when the mirror performs a series of operations to shift from a non-deflection state, placing the mirror in a stationary and non-deflection state, to a predetermined deflection state.

Abstract: A spatial light modulator driven with binary pulse-width-modulation requires very high data transfer rate to achieve high grayscale. This invention enables to reduce substantially the data transfer rate using non-sequential order of binary bits, wherein the combination of the sequences of binary bits is selected from the combinations which avoid simultaneous writing of multiple rows. The possible number of such combinations is astronomically large and mathematical programs were developed to find right combinations. These results were proposed.

Abstract: The present invention provides image projection system implemented with a spatial light modulator, for modulating an illumination light projected from a light source wherein said spatial light modulator comprising an image projection system implemented with a spatial light modulator for modulating an illumination light projected from a light source wherein said spatial light modulator comprising: at least two electrically conductive layers functioning as two different electrical wirings and said conductive layers having respectively a first and a second longitudinal directions overlapping and crossing each other; and a fixed electric potential layer electrically connected to a fixed electric potential, wherein the two different conductive layers and fixed electric potential layer overlapping one another and disposed at a location along a light path of the illumination light emitted from the light source to block said illumination light.

Abstract: A Schottky diode includes a Schottky barrier and a plurality of dopant regions disposed near the Schottky barrier as floating islands to function as PN junctions for preventing a leakage current generated from a reverse voltage. At least a trench opened in a semiconductor substrate with a Schottky barrier material disposed therein constitutes the Schottky barrier. The Schottky barrier material may also be disposed on sidewalls of the trench for constituting the Schottky barrier. The trench may be filled with the Schottky barrier material composed of Ti/TiN or a tungsten metal disposed therein for constituting the Schottky barrier. The trench is opened in a N-type semiconductor substrate and the dopant regions includes P-doped regions disposed under the trench constitute the floating islands. The P-doped floating islands may be formed as vertical arrays under the bottom of the trench.

Abstract: This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.

Abstract: An image display apparatus includes: a first spatial light modulator (SLM) and a second modulator for modulating a first and a second illumination lights for displaying images; an SLM control unit for generating first control data and second control data for controlling the first and second SLMs respectively in accordance with the first and second control data, wherein each of the first control data and second control data is generated for each of a plurality of sub-frame periods divided from one frame period for displaying the images, and the start timing of one sub-frame period of the first control data is different from the start timing of one sub-frame period of the second control data.

Abstract: This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity.

Abstract: This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit for suppressing a transient voltage. The transient voltage suppressing (TVS) circuit includes a Zener diode connected between a ground terminal and a node for triggering a snapback circuit. In one embodiment, this node may be a Vcc terminal. The TVS device further includes a snapback circuit connected in parallel to the Zener diode for conducting a transient voltage current with a snapback current-voltage (I-V) characteristic upon turning on of the snapback circuit And, the TVS device further includes a snapback suppressing circuit connected in series with the snapback circuit for conducting a current with an I-V characteristic complementary to the snapback-IV characteristic for clamping a snapback voltage.

Abstract: An optical character recognition (OCR) system that includes a user-input function for receiving a user input sample for executing said OCR system for optically recognizing a document to generate an output file using the user input sample as a reference.

Abstract: A mirror device comprises: a plurality of electrodes disposed on a substrate; a hinge connected to at least one of the electrodes; a mirror connected to the hinge and corresponding to at least one of the electrodes, wherein a barrier layer is comprised between the hinge and mirror, and/or between the hinge and electrode. Also noted is a mirror device production method for producing such-configured mirror device. Further noted is a projection apparatus comprising such-configured mirror device.

Abstract: This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

Abstract: The present invention discloses a mirror device that includes a mirror element which further comprising an elastic hinge and a mirror and which modulates incident light emitted from a light source, a device substrate on which a drive circuit for driving the mirror element is placed, a package substrate which is made of transparent glass or a silicon material and on which the device substrate is placed, a metallic thermal transfer path connected to the device substrate, and a cover glass connected to the package substrate so that the device substrate is covered.

Abstract: The present invention provides a spatial light modulator, comprising: a pixel array comprises a plurality of pixel units. Each of the pixel units comprises a memory cell. A plurality of word lines and a plurality of plate lines to electrically communicate with the pixel units. A plurality of bit line sets wherein each of the sets includes a pair of bit lines each connected to a memory cell, wherein at least one pair of the memory cells connected to the pair of bit lines are on a same row connected to a same word line.

Abstract: This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of the RC network to prepare for carrying out a wafer-level measurement calibration of the semiconductor power device. The method further includes a step of connecting a probe card to a set of contact pads on the semiconductor wafer for carrying out the wafer-level measurement calibration followed by performing a gate resistance Rg measurement for the semiconductor power chips.

Abstract: This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

Abstract: This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region.

Abstract: A trenched semiconductor power device includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The trenched semiconductor power device further includes a first epitaxial layer above heavily doped substrate and beyond the trench bottom and a second epitaxial layer above said first epitaxial layer wherein a resistivity N1 of said first epitaxial layer is greater than a resistivity N2 of said second epitaxial layer represented by a functional relationship of N1>N2. In an exemplary embodiment, each of the trenched gates include an upper gate portion and lower gate portion formed with single polysilicon deposition processes wherein the lower gate portion is surrounded with a lower gate insulation layer having a greater thickness than an upper gate insulation layer surrounding the upper gate portion.

Abstract: The present invention provides a display apparatus, comprising: an a light source for emitting illumination light for transmitting along illumination light path; a display device includes a plurality of pixels for modulating the illumination light for reflecting the illumination light along a projection light path after said illumination light is modulated by said display device; light path change actuator for changing the projection light paths; and a control circuit for controlling the light source, wherein the control circuit controls the light source in response to changes of the projection light path.