Patents Represented by Attorney, Agent or Law Firm Bo-In Lin
  • Patent number: 7948505
    Abstract: The present invention provides an image signal processor, comprising: (a) an input circuit for receiving and/or holding an image signal of N-bit binary data word, where N is a positive integer; (b) a data converter converting at least M-bit data of binary data into non-binary data having multiple bits, where M is a positive integer and N?M?2, wherein (c) all bits of the non-binary data have a weight which is equal to, or less than, that of the least significant bit of the M-bit data of binary data; and (d) the data converter outputting the each bit of the non-binary data in sequence starting from an equal data value.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: May 24, 2011
    Assignees: Silicon Quest Kabushiki-Kaisha, Olympus Corporation
    Inventors: Kazuma Arai, Fusao Ishii, Yoshihiro Maeda, Hirotoshi Ichikawa
  • Patent number: 7944600
    Abstract: A micromirror device includes an elastic hinge for supporting a mirror on a substrate, and an address electrode for deflecting the mirror. The device further includes a protective layer and an oriented monolayer laid to cover a stopper also functioning as an address electrode provided below the mirror and between the mirror and the substrate.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: May 17, 2011
    Assignees: Silicon Quest Kabushiki-Kaisha, Olympus Corporation
    Inventors: Yoshihiro Maeda, Fusao Ishii, Kazuhiro Watanabe, Hirotoshi Ichikawa
  • Patent number: 7943989
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: May 17, 2011
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Daniel Ng, Lingpeng Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
  • Patent number: 7943424
    Abstract: This invention discloses a method for packaging a semiconductor device with leads extending outside its encapsulation.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: May 17, 2011
    Assignee: Alpha & Omega Semiconductor Incorporated
    Inventors: Limin Wang, Lei Shi, Liang Zhao, Feng Ye
  • Patent number: 7944605
    Abstract: A color display apparatus includes a color changeover unit for changing over colors of an illumination light or a projection light, and a control circuit for applying a video signal for generating a control signal for controlling a spatial light modulator, wherein the control circuit further applying the video signal for generating a control signal during a transition period when the illumination and/or the projection light are projected with a first color coexisting with a second color as the color changeover unit changing over the colors of the illumination light or projection light from the first color to the second color.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: May 17, 2011
    Assignees: Silicon Quest Kabushiki-Kaisha, Olympus Corporation
    Inventors: Taro Endo, Yoshihiro Maeda, Akira Shirai, Fusao Ishii
  • Patent number: 7936011
    Abstract: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: May 3, 2011
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Sik K Lui
  • Patent number: 7933059
    Abstract: The present invention discloses a mirror device that comprises 1) a mirror element for modulating incident light emitted from a light source and for controlling the reflecting direction of incident light, and 2) a coolant flow channel for containing and flowing a liquid coolant through the flow channel to carry away heat generated in the mirror device.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: April 26, 2011
    Assignees: Silicon Quest Kabushiki-Kaisha, Olympus Corporation
    Inventors: Hirokazu Nishino, Yoshihiro Maeda, Fusao Ishii
  • Patent number: 7933102
    Abstract: This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: April 26, 2011
    Assignee: Alpha & Omega Semiconductor, Ltd.
    Inventor: Shekar Mallikararjunaswamy
  • Patent number: 7933060
    Abstract: The present invention provides a spatial light modulator, comprising a mirror modulating a light emitted from a light source, wherein the mirror is further controlled to operate with at least three stationary states whereby an image is projected with a gray scale expression through a combination of modulation of the light operated in the three stationary states.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: April 26, 2011
    Assignees: Silicon Quest Kabushiki-Kaisha, Olympus Corporation
    Inventors: Fusao Ishii, Naoya Sugimoto, Hirotoshi Ichikawa, Yoshihiro Maeda
  • Patent number: 7932148
    Abstract: This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric liner layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: April 26, 2011
    Assignee: Alpha & Omega Semiconductor, Ltd
    Inventors: Hong Chang, Sung-Shan Tai, Tiesheng Li, Yu Wang
  • Patent number: 7929321
    Abstract: A DC-to-DC converter includes a high-side transistor and a low-side transistor wherein the high-side transistor is implemented with a high-side enhancement mode MOSFET. The low side-transistor further includes a low-side enhancement MOSFET shunted with a depletion mode transistor having a gate shorted to a source of the low-side enhancement mode MOSFET. A current transmitting in the DC-to-DC converter within a time-period between T2 and T3 passes through a channel region of the depletion mode MOSFET instead of a built-in diode D2 of the low-side MOSFET transistor. The depletion mode MOSFET further includes trench gates surrounded by body regions with channel regions immediately adjacent to vertical sidewalls of the trench gates wherein the channel regions formed as depletion mode channel regions by dopant ions having electrical conductivity type opposite from a conductivity type of the body regions.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: April 19, 2011
    Assignee: Force-Mos Technology Corp
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7928507
    Abstract: This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: April 19, 2011
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yu Wang, Tiesheng Li, Sung-Shan Tai, Hong Chang
  • Patent number: 7919817
    Abstract: An electrostatic discharge (ESD) protection circuit includes a triggering diode that includes a junction between a P-grade (PG) region and an N-well. The PG region has a dopant profile equivalent to a P-drain dopant profile of a PMOS transistor having a breakdown voltage represented by V whereby the triggering diode for conducting a current when a voltage greater than the breakdown voltage V is applied. In an exemplary embodiment, the dopant profile of the PG region includes two dopant implant profiles that include a shallow implant profile with a higher dopant concentration and a deep implant profile with a lower dopant concentration.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: April 5, 2011
    Assignee: Alpha & Omega Semiconductor Ltd.
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 7916381
    Abstract: A spatial light modulator includes a pixel array including a plurality of pixel elements arranged in a form of a matrix; a word line extending along and connected to a row of the pixel elements pixel elements; and a drive line for transmitting additional modulating signals to said pixel array extended along each row of the pixel array and connected to the pixel elements in a first row and a second row constituting two different rows.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: March 29, 2011
    Assignees: Silicon Quest Kabushiki-Kaisha, Olympus Corporation
    Inventors: Akira Shirai, Fusao Ishii
  • Patent number: 7911680
    Abstract: A mirror device comprises: a plurality of electrodes disposed on a substrate; a hinge connected to at least one of the electrodes; a mirror connected to the hinge and corresponding to at least one of the electrodes. The mirror device further comprises a barrier layer is disposed between the hinge and mirror, and/or between the hinge and electrode. Also noted is a mirror device production method for producing such-configured mirror device. Furthermore, this invention discloses a projection apparatus implemented with a mirror device manufactured and assembled according to the configuration as described.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: March 22, 2011
    Assignees: Silicon Quest Kabushiki-Kaisha, Olympus Corporation
    Inventors: Fusao Ishii, Yoshihiro Maeda, Hirotoshi Ichikawa, Naoya Sugimoto
  • Patent number: 7907320
    Abstract: A micromirror device comprises a plurality of mirrors arranged on a substrate, an elastic hinge for supporting each mirror to be deflectable, an address electrode having first and second regions arranged across the deflection axis of each mirror, a driving circuit for controlling a deflection of the mirror, and a stopper provided in a position of making contact with the mirror in a deflected state of the mirror. When the mirror makes contact with the stopper, the potential of the mirror or the stopper changes.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: March 15, 2011
    Assignees: Silicon Quest Kabushiki-Kaisha, Olympus Corporation
    Inventors: Yoshihiro Maeda, Fusao Ishii, Hirokazu Nishino, Kazuma Arai
  • Patent number: 7907325
    Abstract: A method for controlling a micromirror device including mirror elements each composed of a micromirror supported on a substrate by an elastic hinge, and a address electrode arranged across the deflection axis of the micromirror comprises deflecting the micromirror by changing a potential to a predetermined waveform for the address electrode.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: March 15, 2011
    Assignees: Silicon Quest Kabushiki-Kaisha, Olympus Corporation
    Inventors: Yoshihiro Maeda, Fusao Ishii, Hirokazu Nishino, Kazuma Arai
  • Patent number: 7902604
    Abstract: A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: March 8, 2011
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yi Su, Anup Bhalla, Daniel Ng
  • Patent number: 7901969
    Abstract: A micro-mirror manufacturing method for dividing a plurality of micro-mirror devices each having at least one mirror, formed on a semiconductor wafer into individual micro-mirror devices can be provided. The manufacturing method comprises a step of depositing an inorganic protection layer on the mirror before separating the micro-mirror devices from the wafer and a step of removing the inorganic protection layer after separating the micro-mirror devices from the wafer.
    Type: Grant
    Filed: December 24, 2007
    Date of Patent: March 8, 2011
    Assignees: Silicon Quest Kabushiki-Kaisha, Olympus Corporation
    Inventors: Hirotoshi Ichikawa, Fusao Ishii
  • Patent number: 7893488
    Abstract: This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: February 22, 2011
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventor: François Hébert