Abstract: The present invention provides a spatial light modulator, comprising: a plurality of pixel elements wherein each of the pixel elements comprises at least a switching element; a plurality of control lines connected to at least one of the switching elements; and a controller for generating and transmitting a control signal through the control line for controlling the switching element, wherein the controller starts transmitting the control signal to a first switching element through a first control line before the control signal applied to a second switching element through a second control line is turned off at a low voltage level.

Abstract: The present invention discloses micro-stamp array supported on a substrate comprising a plurality of micro-stamp sticks. Each of the micro-stamp sticks includes a micro-stamp-stick head having a channel opened through a central portion in each of the micro-stamp sticks. Each of the micro-stamp-stick heads is attached to a tapered guide tube surrounded by tapered guide-tube walls wherein the tapered guide tube is in hydraulic communication with the micro-stamp-head channel. The micro-stamp array further includes a filler chip that includes a filler reservoirs disposing on top of the tapered guide tubes, each of the filler reservoirs having a refill channel opened to the tapered guide tube for refilling the tapered guide tube and the channels.

Abstract: A mirror device comprises: an electrode which is covered with a protective film made of a material containing a semiconductor material and is placed on a substrate; a mirror placed above the electrode; and an electrically conductive hinge placed between the mirror and the electrode, wherein an opening part is formed in a part of the protective film, and the hinge penetrates the protective film in the opening part thereof.

Abstract: A micromirror device includes an elastic hinge for supporting a mirror on a substrate, and an address electrode for deflecting the mirror. The device further includes a protective layer and an oriented monolayer laid to cover a stopper also functioning as an address electrode provided below the mirror and between the mirror and the substrate.

Abstract: A public key cryptography (PKI or other similar system) is used to sent partial or multiple of encryption or decryption algorithm (cipher or decipher) to the data sender or receiver to encrypt or decrypt the data to be sent or received and destroy itself after each or multiple use. Since the encryption algorithm is protected, it can be devised very small in size in compare to the data to be sent and the user can afford to use large key size in it's transmission to increase protection without significant compact to the overall speed. Without knowing the encryption algorithm, which may also be changing from time to time, it will be impossible to use brut force to break the code provided that the algorithm scheme is designed properly. It is due to that there are unlimited numbers of new or old algorithms with countless variations and it takes years of supper fast computing time to break even few algorithms.

Abstract: A micromirror device, which makes an image display with digital image data, comprises pixel elements which are arranged in the form of a matrix and each of which modulates incident light by using an ON state for deflecting incident light to projection optics, an OFF state for deflecting incident light to a direction different from the projection optics, and an oscillation state where a mirror oscillates between the ON and the OFF state, and a timing controller for performing a timing control for loading the image data into the pixel elements arranged in the form of the matrix. Each of the pixel elements has a mirror, and at least one memory cell. The pixel elements arranged in the form of the matrix are grouped into a plurality of subsets. The timing controller performs a timing control for loading the image data at independent timing for each of the plurality of subsets.

Abstract: An electronic package for containing at least a top packaging module vertically stacked on a bottom packaging module. Each of the packaging modules includes a semiconductor chip packaged and connected by via connectors and connectors disposed on a laminated board fabricated with a standard printed-circuit board process wherein the top and bottom packaging module further configured as a surface mountable modules for conveniently stacking and mounting to prearranged electrical contacts without using a leadframe. At least one of the top and bottom packaging modules is a multi-chip module (MCM) containing at least two semiconductor chips. At least one of the top and bottom packaging modules includes a ball grid array (BGA) for surface mounting onto the prearranged electrical contacts. At least one of the top and bottom packaging modules includes a plurality of solder bumps on one of the semiconductor chips for surface mounting onto the prearranged electrical contacts.

Abstract: An electronic circuit includes a filtering circuit implemented with a distributed inductor-and-capacitor (LC) network that includes metal oxide effect (MOS) trenches opened in a semiconductor substrate filled with dielectric material for functioning as capacitors for the distributed LC network. The electronic circuit further includes a transient voltage suppressing (TVS) circuit integrated with the filtering circuit that functions as a low pass filter wherein the TVS circuit includes a bipolar transistor triggered by a diode disposed in the semiconductor substrate. The distributed LC network further includes metal coils to function as inductors disposed on a top surface of the semiconductor electrically contacting the MOS trenches.

Abstract: This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by manufacturing a MOSFET with a higher gate work function by implementing a P-doped gate in an N-MOSFET device. The P-type gate increases the threshold voltage and shifts the C-Vds characteristics. The reduced Cgd thus achieves the purpose of suppressing the shoot through and resolve the difficulties discussed above. Unlike the conventional techniques, the reduction of the capacitance Cgd is achieved without requiring complicated fabrication processes and control of the recess electrode.

Abstract: The present invention provides a mirror device, comprising: a plurality of deflectable mirrors; an elastic member for supporting the mirror and to deflect the mirror to a range of deflecting angles; a drive electrode for driving the mirror; a control circuit for giving electric charge to the drive electrode and controlling the deflecting direction of the mirror; and a substrate on which the drive electrode and the elastic member, wherein the drive electrode is placed within an area on the substrate the mirror is projected on, has an outer form constituted by sides approximately in parallel to the outer peripheral lines of the present mirror and by sides approximately parallel to the deflection axis of the present mirror, or a form obtained by dividing the aforementioned outer form into a plurality thereof, and also fills the role of a stopper for regulating the deflection angle of the mirror.

Abstract: A MOSFET with a 0.7˜2.0 micrometers deep trench is formed by first carrying out a processing step of opening a trench in a semiconductor substrate. A thick insulator layer is then deposited in the trench such that the film at the bottom of the trench is much thicker than the sidewall of the trench. The insulator layer at the sidewall is then removed followed by the creation of composite dual layers that form the Gate Oxide. Another embodiment has the insulator layer deposited after Gate Oxide growth and stop at a thin Nitride layer which serves as stop layer during insulator pullback at trench sidewall and during Polysilicon CMP. Embodiments of the present invention eliminates weak spot at trench bottom corner encountered when Gate Oxide is grown in a 0.2 micrometers deep trench with thick bottom oxide.

Abstract: A semiconductor power device supported on a semiconductor substrate of a first conductivity type with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer with a same conductivity type as the bottom layer. The semiconductor power device includes a plurality of FET cells and each cell further includes a body region of a second conductivity type extending from a top surface into the epitaxial layer. The body region encompasses a heavy body dopant region of second conductivity type. An insulated gate is disposed on the top surface of the epitaxial layer, overlapping a first portion of the body region. A barrier control layer is disposed on the top surface of the epitaxial layer next to the body region away from the insulated gate. A conductive layer overlies the top surface of the epitaxial layer covering a second portion of the body region and the heavy body dopant region extending over the barrier control layer forming a Schottky junction diode.

Abstract: A semiconductor power device is formed on a semiconductor substrate. The semiconductor power device includes a plurality of transistor cells distributed over different areas having varying amount of ballasting resistances depending on a local thermal dissipation in each of the different areas. An exemplary embodiment has the transistor cells with a lower ballasting resistance formed near a peripheral area and the transistor cells having a higher ballasting resistance are formed near a bond pad area. Another exemplary embodiment comprises cells with a highest ballasting resistance formed in an area around a wire-bonding pad, the transistor cells having a lower resistance are formed underneath the wire-bonding pad connected to bonding wires for dissipating heat and the transistor cells having a lowest ballasting resistance are formed in an areas away from the bonding pad.

Abstract: A novel integration scheme for forming power MOSFET, particularly forming salicides for both gate and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicides.

Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

Abstract: A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the first and second stages JFET is connected to a drain electrode of another JFET stage.

Abstract: This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage.

Abstract: A TSOP (Thin Small Outline Package) contains a MOSFET and a Schottky diode. The MOSFET has a source terminal a gate terminal and a drain terminal. The Schottky diode has a cathode terminal, a anode terminal. The TSOP contains the MOSFET and the Schottky diode with a special configuration by placing the drain terminal of the MOSFET and the anode terminal of the Schottky diode on a same side. Specifically, the TSOP implements a leadframe that comprises a plurality of leads. The drain terminal of the MOSFET and the anode terminal extends outside of the TSOP separate on the same side of the package.

Abstract: The present invention provides an image projection system comprising a spatial light modulator (SLM) comprises a plurality of pixel elements, wherein each of the pixel elements further comprises a deflectable mirror, and at least a first electrode and a second electrode for controlling the deflectable mirror to deflect to different tilt angles to reflect and modulate an illumination light for displaying an image; and a controller for applying a voltage to the second electrode wherein the voltage applied in an initial operation period is different from the voltage applied in an image display period.

Abstract: This invention discloses a method for manufacturing a one-time programmable (OTP) memory includes a first and second MOS transistors connected in parallel and controlled by a common gate formed with a single polysilicon stripe. The method further comprises a step of implanting a drift region in a substrate region below a drain and source of the first and second MOS transistors counter doping a lightly dope drain (LDD) encompassing and surrounding a drain and a source of the first MOS transistor having a different threshold voltage than the second MOS transistor not reached by the drift region.