Abstract: A mirror device, comprising: a mirror; an electrode which is placed on a substrate and on which surface a cavity is formed; and a hinge placed between the mirror and electrode, wherein the hinge is connected to the cavity of the electrode.

Abstract: This invention discloses a semiconductor power device disposed on a semiconductor substrate supporting an epitaxial layer as a drift region composed of an epitaxial layer. The semiconductor power device further includes a super-junction structure includes a plurality of doped sidewall columns disposed in a multiple of epitaxial layers. The epitaxial layer have a plurality of trenches opened and filled with the multiple epitaxial layer therein with the doped columns disposed along sidewalls of the trenches disposed in the multiple of epitaxial layers.

Abstract: This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region.

Abstract: A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.

Abstract: A resetable over-current self-protecting semiconductor power device comprises a vertical power semiconductor chip and an over-current protection layer composed of current limiting material such as a PTC material. The over-current protection layer may be sandwiched between the vertical power semiconductor chip and a conductive plate, which could be a leadframe, a metal plate, a PCB plate or a PCB that the device is mounted on.

Abstract: A micromirror device, which makes an image display with digital image data, comprises pixel elements each of which makes pulse width modulation for incident light depending on the deflection state of light and which are arranged in the form of a matrix. Each of the pixel elements has a mirror, and at least one memory cell comprising a transistor and a capacitor. In such a micromirror device, the total value of the propagation delay time of a ROW line, which connects all of transistors of memory cells arranged successively in a ROW direction, and the switching time of each transistor is smaller than the driving interval of the ROW line driven in the minimum display duration of the micromirror device.

Abstract: A micromirror device, which makes an image display with digital image data, comprises pixel elements each of which makes pulse width modulation for incident light depending on the deflection state of light and which are arranged in the form of an array. The array of the pixel elements is composed of B subsets each including pixel elements of Ms (COLUMNs)×Ns (ROWs) (Ms, Ns, and B are natural numbers). Each of the pixel elements has a mirror, and at least one memory cell. The memory cell has a transistor of an input gate capacity Ct[F]. Each memory cell is connected by a ROW line having a wiring resistance R[?], and a wiring capacity C[F]. When a gray scale display of 10 [bits] or more for each color is made with a color sequential display of C0 colors, Ms, Ns, B, Ct, R, C, and C0 have a relationship of R*(Ct+C)<(1.63*10?5*B)/[Co*Ms*Ns*(Ms+1)].

Abstract: This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path.

Abstract: The present invention provides a spatial light modulator, comprising: a plurality of pixel units configured as a pixel array wherein each of the pixel units further comprises a memory circuit. The spatial light modulator further includes a bit line for transmitting a data signal to the memory circuit. The spatial light modulator further includes a word line for selecting and writing the data signal to the selected memory circuit. The spatial light modulator further includes a plate line for controlling the memory; and an address decoder for selecting the plate line, wherein the address decoder comprises an address judgment unit constituted by a plurality of first judgment units and further includes a second judgment unit for changing an output from the second judgment unit depending on a result generated by the first judgment unit.

Abstract: The present invention discloses a spatial light modulator includes a plurality of pixel elements disposed on a substrate. Each of the pixel elements comprises a deflectable micromirror. Specifically, instead of SRAM, the spatial light modulator is implemented with a DRAM in each of the pixel elements. The DRAM in each of the pixel elements has a smaller number of transistors than SRAM. The spatial light modulator can be manufactured with smaller pixel size and circuit configuration with improved withstand voltage. Further improvements can also be achieved for manufactured the spatial light modulator with smaller capacitor with better layout configuration for wire connections and control signal transmissions.

Abstract: A micromirror device, which makes an image display with digital image data, comprises pixel elements each of which makes pulse width modulation (PWM) for incident light depending on the deflection state of light and which are arranged in the form of a matrix. Each of the pixel elements has a mirror, at least one memory cell comprising a transistor and a capacitor, and an electrode connected to each transistor. Memory cells arranged successively in a ROW direction are connected by a ROW line. The image data is loaded at a time interval during which the voltage of the electrode can hold the deflection state of a pixel element.

Abstract: An image display apparatus is disclosed in this invention. The image display apparatus includes a light source for emitting an illumination light, at least one spatial light modulator for receiving and applying an image signal for modulating illumination light from the light source, and a control circuit for controlling the light source and/or the spatial light modulator to project a modulated light for image display having different gray scale characteristics between at least two successive frames.

Abstract: A display system includes a spatial light modulator for displaying a image by the modulation state of a plurality of micromirrors, and a control device for controlling the spatial light modulator. The control device includes a data conversion device for converting the digital image data into non-binary data, and a modulation-control device for generating a modulation control signal for micromirrors depending on the non-binary data, and controlling the spatial light modulator. The modulation state of the micromirrors by the modulation control signal includes modulation by oscillation of the micromirrors. The modulation control signal controls amplitude of the oscillation to be smaller than the maximum amplitude of the micromirrors in the modulation by the oscillation of the micromirrors. The oscillation having smaller amplitude than the maximum amplitude of the micromirrors is repeated by the modulation control signal in an optional time duration or frequency.

Abstract: A semiconductor power device formed on a semiconductor substrate of a first conductivity type wherein the semiconductor power device includes trench gates surrounded by body regions of a second conductivity type encompassing source regions of the first conductivity type therein. The semiconductor power device further includes trench contact structure having a plurality of trench contacts with trenches extended into the body regions for as source-body contacts and extended into the trench gates as gate contact. The semiconductor power device further includes a termination area wherein a plurality of the trench gate contacts are electrically connected to the source-body contacts.

Abstract: This invention discloses a new trenched vertical semiconductor power device that includes a capacitor formed between a conductive layer covering over an inter-dielectric layer disposed on top of a trenched gate. In a specific embodiment, the trenched vertical semiconductor power device may be a trenched metal oxide semiconductor field effect transistor (MOSFET) power device. The trenched gate is a trenched polysilicon gate and the conductive layer is a second polysilicon layer covering an inter-poly dielectric layer disposed on top of the trenched polysilicon gate. The conductive layer is further connected to a source of the vertical power device.

Abstract: A mirror device including: a mirror arranged on a substrate, supported by a hinge, and arranged substantially parallel to the substrate; a plurality of address electrodes for deflecting the mirror to an ON state, an OFF state, or an oscillating state; and a drive circuit for applying a voltage to the plurality of address electrodes. The mirror device is controlled such that a voltage can be applied to a corresponding address electrode to deflect the mirror, and oscillation in the oscillating state can be started from a state of the deflected mirror.

Abstract: The present invention provides an image display system implemented with a mirror device comprises a plurality of pixel elements formed on a substrate: wherein: each of said pixel elements comprises a micromirror disposed above and supported on a hinge extended from said substrate; and; a drive electrode disposed on the substrate for receiving signals to control and drive the mirror, wherein the drive electrode comprises an insulation layer, and a first electrode connected to a memory and a second electrode connected to a plate line with the insulation layer disposed between and insulating the first and the second electrode.

Abstract: A video image display apparatus for displaying a video image in accordance with a video image signal including: a light source for emitting an illumination light to a color wheel driven by a color wheel driving unit to rotate the color wheel for filtering and transmitting lights of different colors therefrom; a spatial light modulator (SLM) for receiving the lights of different colors projected from the color wheel; a master clock signal generation unit for generating a master clock signal constituting a reference for transferring data to the SLM; a frame start signal generation unit for generating, from the master clock signal, a frame start signal indicating the start of a frame; a wheel position detection unit for detecting an angular position of the wheel; a phase comparison unit for comparing a phase of the frame start signal with a wheel index signal generated from the wheel position detection unit indicating a position of the color wheel; and a motor control unit for receiving a phase comparison signal

Abstract: A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.

Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.