Abstract: A multi-chip module development substrate (12) contains embedded test circuitry (30). Vias (38) connect I/O channels (Cn) of the test circuitry with conductive runs in interconnect layers (16,18) that are part of an interconnect structure (17) of the development substrate. Integrated circuit chips (14) are then mounted on the multi-chip module development substrate in selected electrical contact with the conductive runs. The embedded test circuitry includes multiple timing analyzer circuits (TAn) and multiple analog probe circuits en). In a preferred embodiment, these timing analyzer circuits and analog probe circuits are provided in redundant pairs, with a pair of each associated with each of the I/O channels. Multiple pairs of each kind of circuit are grouped within test cells (70) physically arranged in rectangular areas. Adjacent test circuit cells may be rotated with respect to each other to achieve more efficient connections to interconnect structure.
Abstract: Methods for producing logic signal displays for an instrument known as a "logic oscilloscope" are disclosed. A digital input signal is first sampled as an analog signal to produce multi-bit digital samples that are representative of the amplitude of the input signal over time. The multi-bit digital samples are then processed using interpolative techniques to ascertain when the input signal crossed a hypothetical logic level threshold or pair of thresholds and when the signal was in one logic state or the other. The resulting transition times and logic states are then used as the basis for generating a variety of digital displays, including logic timing diagrams, state table displays, and cursor readouts similar to those available in a logic analyzer. Setup and hold time violations and measurements may also be obtained using this information.
Abstract: An oscilloscope comprises a trigger circuit for initiating display of the waveform of an input signal in response to a trigger event, at least one detection circuit responsive to the input signal for detecting occurrence of an anomalous event therein, and a counter for reporting the number of occurrences of the anomalous event that have been detected.
Abstract: An electronic instrument with a housing having a battery compartment. The housing has a probe connector oriented on a probe axis, so that a probe may be connected to the instrument via the connector for interfacing with a device under test. A removable battery cover encloses the battery compartment, and has a probe aperture registered with the probe connector, so that a probe may be connected when the battery cover is installed. To prevent removal of the battery cover when a probe is connected to the probe connector, the battery cover is constrained against movement along the probe axis. In addition, the battery cover may contain a conductive safety element necessary to complete a circuit between the battery and other components in the instrument, so that the batteries are capable of delivering power only when the cover is properly installed.
Abstract: A differential attenuator is described that is capable of automatic calibration using electronically adjustable circuit elements. The differential attenuator has positive and negative inputs and outputs. A resistor and capacitor couple the positive side input and output, while a matching resistor and capacitor couple the negative side input and output. Shunt resistors and shunt capacitors coupled to the positive and negative outputs are augmented and made electronically adjustable by multipliers having their signal inputs coupled to the respective side output nodes. The outputs of one set of multipliers are coupled to the other ends of the shunt resistors, while their multiplication coefficients are controlled by a dc.sub.-- control signal. The outputs of another set of multipliers are capacitively coupled back to their respective side output nodes, while their multiplication coefficients are controlled by an ac.sub.-- control signal.
Abstract: A method for evaluating an electrical signal is disclosed. This method is especially useful for evaluating analog signals within an integrated circuit or other inaccessible location. A reference histogram is derived from either a simulation of a desired waveform or from sampling a desired waveform signal. This reference histogram is subtracted from a test results histogram to produce a variance histogram. The variance histogram can be further evaluated to determine characteristics of the electrical signal under test and/or to produce a figure of merit for the circuitry producing the signal under evaluation. Before the difference between the test results histogram and the reference histogram is taken, normalization, offset calculation, gain adjustment, and noise floor adjustment may be performed on the test results histogram, and these values may be exported to further aid in characterization of the signal under evaluation.
Abstract: An embedded electronic system includes a clock controller embedded in the same matrix material as a subsystem under test and the measurement devices needed to test it. This embedded clock controller controls the distribution and gating of a system clock that runs continuously, but is only supplied to the subsystem under test during normal operation or during pre-programmed intervals of testing operations. A test data bus supplies test data and a path for the return of test results. The test data supplied to the clock controller includes information to control time relationships between its trigger and gated clock outputs. Different versions of the clock controller are described, one for use with a serial test data bus and another for use with a parallel test data bus. The clock controller can also be configured to produce trigger signals with timing appropriate to operating either edge-sensitive or level-sensitive measurement devices.
Abstract: An adjustable precision delay circuit includes a series of inverter gates and a multiplexer for selecting any of their outputs or the input to the series. The polarity of the signal input to this circuit is controlled so that any selected output always has the same predetermined polarity, thereby eliminating timing errors arising from factors that vary with the polarity of the output.
Abstract: A high bandwidth amplifier circuit with input protection is achieved by providing a signal limiting diode circuit in the path to the positive input of the amplifier and a cross-over signal feed path for coupling a portion of the input signal from the input signal source side of the signal limiting diode circuit to the negative input of the amplifier. To maximize the overall circuit bandwidth and minimize VSWR and noise, the cross-over signal feed path is designed to couple over to the negative input of the amplifier a signal that has at a higher-end of the bandwidth range an increasing amplitude and increasingly leading phase relationship relative to the amplitude limited version of the input signal being coupled to the positive input of the amplifier. In a desirable embodiment, most of the circuitry is contained on an integrated circuit and bond wires needed for coupling serve as inductors and tune the circuitry.
Abstract: A high-frequency calibration method and circuit including a dual path step attenuator. A calibration system is provided having a switch between the user signal input and the instrument input and an amplifier between the calibration signal input and the instrument input. The amplifier provides signal conditioning. The output of the amplifier is connected to the instrument input through a switch and a resistor, the resistor isolating the switch from the instrument input so as effectively to prevent degradation of the user input signal. A sense amplifier provides a calibration signal output indicative of the input impedance of the instrument input in response to a known stimulus. The input of the sense amplifier is isolated from the instrument input by a resistor. A current source provides a known stimulus to the instrument input to measure input impedance. A step attenuator is provided having an attenuated path and an unattenuated path.
Abstract: A circuit modifies a fast-in, slow-out data acquisition system to provide a redundant analog data acquisition cell (aR) that can be substituted for a defective cell without adversely affecting the timing between acquired samples. This circuit includes a plurality of signal acquisition cells (a1-an) including at least one redundant cell arranged in a row, a source of sample and hold clock signals (b1-bn) for the signal acquisition cells, and a corresponding row of demultiplexers (D1-Dn). Each acquisition cell has an analog signal input and a sample and hold clock signal input that determines when the analog signal is to be sampled. The demultiplexers each have a signal input, a select input, and at least two outputs, with the input being coupled to one of the sample and hold clock signals, and the outputs being coupled to the sample and hold clock inputs of two adjacent signal acquisition cells.
Abstract: A visually graded display of digitally compressed waveforms for a digital storage oscilloscope. A histogram is formed by sampling or otherwise resolving a data set of values corresponding to an independent variable to produce a quantized set of values over a selected compression interval of the independent variable. The compression interval represents equal quanta of the independent variable and has associated therewith a set of histogram bins, each containing a number, wherein the number contained within each bin represents a weighted number of hits associated with vectors connecting selected pairs of such dependent variable values, wherein each vector is associated uniquely with one pair. The numbers are weighted for each vector according to drawing techniques, the drawing techniques alone or in combination allowing choices for signal display ranging between retaining maximal signal information, for emulating the display of an analog oscilloscope, or retaining less signal information.
Abstract: A hybrid R-C component for use in oscilloscope probes of the type having a resistive element disposed on a first surface of a substrate, and having a first conductive coating disposed on a second surface of the substrate, and having a dielectric layer disposed over the first conductive coating, a second conductive coating partially disposed over a first portion of the substrate and in contact with a first end of the resistive element and with a region of the second conductive coating being partially disposed over the dielectric layer and forming a first capacitor plate, a third conductive coating disposed over a second portion of the substrate and in contact with a second end of the resistive element and with a region of the third conductive coating being partially disposed over the dielectric layer and forming a second capacitor plate, whereby the first capacitor plate and a first area of the first conductive coating in conjunction with the dielectric layer form a first capacitor C1 and the second capacitor
Abstract: A trigger system for a digital oscilloscope operating in external clock mode. Every n pulses, the trigger system generates a trigger signal. The trigger system therefore provides a trigger every n samples of the input signal waveform.
Abstract: To increase the percentage of time that an input signal is actively monitored, a digital oscilloscope has an acquisition system (100) that includes an analog-to-digital converter (15), an acquisition memory (40), an acquisition rasterizer (50), and a raster acquisition memory (60). The rasterizer contains circuitry (52) for concurrently rasterizing and combining the results of several acquisitions together and with a stored composite raster image to produce a new composite raster image, while additional acquisition records are being created and stored in the acquisition memory. A display system (200) takes the composite raster images after they contain the results of many acquisitions and overlays these single-bit raster images on a multi-bit raster image that is then decremented to produce a simulated persistence effect.
April 13, 1994
Date of Patent:
June 25, 1996
Eric P. Etheridge, Gordon W. Shank, Daniel G. Knierim
Abstract: A modular instrumentation system with a chassis having a number of module slots and having a plenum providing airflow to the slots. A ventilator connected to the chassis blows air into the plenum. A number of dampers are connected to the chassis, each adjacent a respective module slot and movable between a closed position blocking airflow between the plenum and the module slot, and an open position permitting airflow between the plenum and the module slot. Each damper is biased to the closed position and automatically moves to the open position in response to installation of a module in the module slot.
Abstract: A logic analyzer acquires all data and clock signal inputs asynchronously at high speed using a digital FISO (10) to produce a plurality of parallel high-speed data samples within each cycle of an internal system clock (95). The plurality of parallel high-speed data samples describe the sequential behavior of one of the input signals during one period of the internal system clock. One of the plurality of parallel high-speed data samples is then selected to be the single data sample that is stored in the acquisition memory (80) for that clock cycle. The selection process includes a skew adjustment (20), clock edge detection and selection (50), aligning the sample associated with the detected and selected clock edge to a reference location (60), and selecting (70) as the single sample to be stored a sample having a relationship to the reference location that is determined by setup and hold adjustment data.
February 16, 1994
Date of Patent:
June 11, 1996
Tim E. Sauerwein, Craig L. Overhage, Donald C. Kirkpatrick
Abstract: A high-speed data acquisition and processing system. The system includes a sequential sampler that samples an input signal at periodic intervals. The resulting samples are provided on a plurality of sample outputs. These sample outputs are received by a matrix of signal processors, each of which receives and processes at least two inputs, and provides a processor output. The first row of signal processors receives the sample outputs and processes them. Subsequent rows of signal processors receive and process the outputs of signal processors in previous rows.
Abstract: A digital oscilloscope of the type that processes (30) the digital waveform values of the waveform record using interpolation and/or decimation (81) to produce a main trace record (91) and first (92) and second (93) zoomed trace records, and uses those records to produce (40) a main trace display (65) and first (61) and second (62) zoomed trace displays is improved by providing (94) a first zoom box (63) encompassing that portion of the main trace (65) display shown in the first zoomed trace (61) display and a second zoom box (64) encompassing that portion of the main trace (65) display shown in the second zoomed trace (62) display.
Abstract: A time-interleaved method for efficient operation of an acoustic wave sensor array couples each sensor repetitively and one at a time via a digitally-addressable analog switch, or multiplexer, to a single oscillator driver to form an oscillation circuit. A frequency of oscillation for each acoustic wave sensor is determined. The frequency for each acoustic wave sensor then is converted into a measurement value for the parameter to which each acoustic wave sensor is sensitive.