Abstract: A deformable connector provides a concentrated wiping action pressure during the connection process, yet forms a flat mating surface when it is fully mated, and that is also suitable for providing a double density connection between a printed circuit board and a flexible circuit cable, as well as other applications. The connector includes an elastomeric member whose lower surface has a first convex region at one end, a second convex region at the other end, and a concave region in a middle joining the first and second convex regions. The upper surface contains a convex region in its middle that is approximately parallel to the concave region of the lower surface, producing an approximately constant thickness over most of the length of the elastomeric member, thus forming a flat mating surface in its fully mated condition. Conductive runs to be connected to a mating surface are disposed on the lower surface of a flexible circuit or cable affixed to the lower surface of the elastomeric member.

Abstract: A method for producing a statistical profile of a repetitive electrical signal entails selecting a window pulse width that is preferably a large multiple of the period of the signal, setting a comparison threshold, and counting the time that the signal is above (or below) the comparison threshold during the window pulse. The comparison threshold is then repeatedly incremented (or decremented) over the amplitude range of the signal, while this procedure is repeated at each level. The difference is then taken between the times measured at adjacent amplitude increments and the absolute value of these differences is displayed as the waveform profile. An apparatus for implementing this method includes a counter/timer, a gate, a comparator, a pulse generation circuit, a comparison threshold generation circuit, and a microprocessor for controlling the other circuit elements and performing calculations.

Abstract: A logic analyzer has a counter/timer that can reconstruct the higher resolution with which data was acquired using multiple phases of the logic analyzer system clock signal. For a two-phase data sampling system, separate pairs of event recognizers monitor the data collected using the two phases of the system clock. Counter/timer control logic uses the information from these separate pairs of event recognizers to control the behavior of the counter/timer so that it can either single count or double count, depending on whether an event was true during both phases or only one phase of the data acquisition, thus allowing the counter/timer resolution to be as high as the information inherent in the data acquired using both clock phases. The counter/timer employed is capable of single or double counting and has two stages, a prescaler and an extension counter/timer, for increased power and cost effectiveness.

Abstract: A circuit allows digital data acquisition instruments to recognize when dual threshold synchronous data being monitored in unstable. Each data line being monitored for unstable periods is compared with a high threshold level and a low threshold level at an acquisition probe and the results of these two comparisons are forwarded to the circuit of the present invention. Optionally, a glitch latch may be employed to cause transient crossings of the threshold to be treated as if they lasted until the next clock. The two bits of resulting information are each clocked through a short shift register consisting of two flip-flops. A gate monitoring each of these short shift registers produces an active output when the state of the two flip-flops indicates that the signal left the high state or left the low state. A third gate monitors the last flip-flop in each short register to produce an active output when the signal is neither high nor low.

Abstract: A data transfer synchronization method and circuit allows data to be transferred between two synchronous systems running asynchronously with each other in a way that does not require the receiving system clock to be running twice as fast as the source system clock. Data is clocked into a first set of flip-flops by the clock signal of the source system. The source system clock signal is also used to toggle a toggle flip-flop. The receiving system clock signal is used to clock a first clock bit flip-flop coupled to detect the state of the toggle flip-flop. A delayed version of the receiving system clock signal is used to clock the output of the first set of flip-flops into a second set of flip-flops. The normal (undelayed) receiving system clock signal is used to clock the output of the second set of flip-flops into a third set of flip-flops.

Abstract: A circuit board is fabricated from first and second composite sheets, each composed of a substrate of dielectric material and at least one conductor run adhered to the substrate. The substrate of the second composite sheet is formed with a through hole adjacent to the conductor run of that sheet. The second composite sheet is adhered to the first composite sheet, with the conductor run of the first sheet exposed through the hole in the second sheet. Conductive material is introduced into the hole and provides an electrically-conductive connection between the conductor runs of the two sheets.

Abstract: A method for distinguishing between real and spurious responses in a swept frequency spectrum analyzer in a convenient and on-going way uses sweep data from two different, but equivalent, paths through the spectrum analyzer front end. The setup of the spectrum analyzer front end continuously alternates between the first and second of these setups. A sweep of the spectrum using the first setup is digitized and stored, as well as displayed. The sweep obtained using the second setup is also digitized and stored, as well as displayed. However, at the same time that the current sweep data is being displayed, the stored sweep data from the previous sweep using the other setup is also displayed at the same location on the screen. At anyone time, there are two displays on the screen, overlaid with each other as exactly as possible.

Abstract: A connection apparatus for interactively accessing over signal paths of minimum length the signals by which an electronic device with a large number of pins communicates with its environment through a pin grid array socket includes two printed circuit boards, each having a pin grid array socket or a plurality of individual receptacles for pins arranged in a pin grid array pattern, stacked vertically with their pin grid arrays vertically aligned. Each of these circuit boards has a receptacle side on top and a partial array of associated pins on the bottom.

Abstract: A synchronous programmable binary counter has a parallel section and a serial section, with the length (in bits) of the serial section being the same as the modulus of the parallel section. The parallel section counts on system clocks and produces two outputs. A parallel terminal count output is produced each time the parallel section count reaches a programmed value. A frame output is generated every time the parallel section reaches its maximum count and starts counting again. The serial counter section decrements its programmed value by one each time it receives a frame signal from the parallel section. This subtraction is accomplished by a half-adder and associated borrow flip-flop. The borrow flip-flop is set by each arrival of the frame signal. Between frame signals, the decremented programmed value is circulated in a shift register as the serial subtraction process is performed.

Abstract: A multiphase memory array is read out using two multiplexers and a demultiplexer under the control of a state machine. The state machine enables one portion of the memory array at a time using a gate to multiplex the memory portion outputs. While a particular portion is enabled, a bit multiplexer associated with that portion is directed by the controlling state machine to sequentially select each bit at the current address in that memory portion for output. A shift register demultiplexer performs serial to parallel conversion on the sequential bits from each memory portion to convert them to a readback byte or word for output. After the byte or word has been read out, the state machine enables the next portion of the memory array and repeats the multiplexing and demultiplexing process for the data at the same address in that memory portion. When all of the memory portions have read out, the address to the memory array is changed and the whole process is repeated for the data at the new address.

Abstract: An improved shift register uses fewer than 2*N latches, where N is the capacity in bits of the shift register and also the propagation delay from the input to the output of the shift register in terms of the system clock. An m-phase set of clocks are used, where m is an even number larger than two and and the duration of each clock phase is one half of the period of the system clock. The latches are arranged in m/2 strings of length 2N/(m-1), instead of one long string. The strings of latches are offset with respect to each other by two phases in terms of their connection to the multiphase clock, with each successive latch in each string being enabled by the clock signal whose phase immediatedly precedes the phase of the clock signal used to enable the preceding latch in that string. A multiplexer at the output puts the data from the multiple strings of latches back into one serial output stream.

Abstract: An apparatus and method of using markers for identifying particular points on a quasi-3-dimensional display, such as a color spectrogram display or a waterfall display of multiple frequency spectra on an electronic spectrum analyzer, so that amplitude, time, and frequency values associated with a particular point can be conveniently read out, and so that differences in amplitude, time, and frequency between two points can be easily calculated and presented to the user. Two markers whose positions are ascertainable are generated on the quasi-3-dimensional display and are made subject to operator control. One of these markers is positioned by the operator on a particular point of interest and the values associated with that location are then displayed for readout with greater precision and convenience than would otherwise be possible. A second marker is placed at a second point of interest and the differences in the values of amplitude, time, and frequency between the two points are calculated and displayed.

Abstract: Methods and circuits for implementing them determine the phase angle of a complex electrical signal from the in-phase and quadrature components of the signal by truncating the magnitudes of the real and imaginary components of the signal and combining them to form an address which is then used to access a lookup table containing angular values. However, if both of the values are small, before they are truncated they are both expressed in terms of a lowest common exponent, i.e., shifted left as much as possible without affecting their ratio. The phase angle from -180 to +180 degrees may be found directly from the lookup table, or, in an alternative variation on the method, a single-quadrant angle is looked up in a shorter table and then supplemented according to quadrant information contained in the signs of the values to produce the total phase angle. Circuits are disclosed for implementing both methods for inputs in 2's complement or sign and magnitude form.

Abstract: A programmable counter or timer is preloaded with a value that serves to discriminate between meaningful transitions and spurious ones, and an output latch is initialized so that the value it contains is equal to the initial value of a comparator output. The binary output of the comparator is then continuously compared with the content of the output latch. If the two values become unequal, indicating a change in the state of the comparator output, the timer or counter is enabled to start timing or counting. If the change in the comparator output lasts long enough to qualify the transition as meaningful, the timer/counter times out clocking the new comparator output condition into the output latch.

Abstract: A user interface for a tester or simulator includes a menu for creating templates. The templates organize a set of the user's decisions regarding the timing, direction, and masking of all of the signals occurring during one tester cycle into a convenient form for use in another menu where test vectors are actually specified. In this other menu, the templates serve as a shorthand way of describing the function of each channel and its timing characteristics during one tester cycle. Thus, these templates organize and simplify the user's decision making, since many decisions, that would otherwise have to be made again and again, may now be made only once and then incorporated again and again by reference to the appropriate template. The use of the templates also conserves total memory requirements. The template menu can provide visual feedback that includes timing diagrams and icons to assist the user in constructing the template.

Abstract: A multiple digital event generator produces events with timing that is programmable, yet the event generator requires a minimum of circuitry for its construction and is capable of operating at very high speeds. A linear feedback shift register is used to produce an arbitrary sequence of non-repeating binary numbers. These numbers are then monitored by one or more digital comparators whose other digital input is chosen so as to cause the desired event to occur when a certain number in the number sequence occurs. The minimum time between events and the maximum range of event control timing is adjustable by varying the frequency of the clock input to the linear feedback shift register. Maximum speed is achieved by using one set of the shift register flip-flop outputs (Q or Q-not) for internal feedback and the other set (Q-not or Q) for the output to the digital comparators, so that the speed of operation of the shift register is not degraded by the load of the multiple digital comparator circuits on its output.

Abstract: A ferrimagnetic resonator has improved high frequency response because a shorter, tapered pole shaft is substituted for the longer pole shafts of uniform dimensions in the prior art. This shorter, tapered shaft alleviates constrictions in the field of the magnetic flux, thus allowing for an improved flux density at the tip of the magnet and correspondingly improved high frequency operation of the ferrimagnetic resonator. In a preferred embodiment, the tip of the pole is replaced with a layer of a higher permeability, but also higher hysteresis, alloy to improve the flux density in the air gap where the ferrimagnetic crystal resonator elements reside. In alternative embodiments, the case end of the pole shaft can attain its greater dimensions because of sides that curve outward or that get larger in a series of steps.

Abstract: A pin driver circuit for driving a digital integrated circuit is capable of producing symmetrical rise and fall characteristics, yet is suitable for implementation in monolithic bipolar integrated circuits. This circuit includes a pair of matched transconductance amplifiers, one at each end of an output resistor, connected between a voltage source and a return voltage. Each amplifier has one of a pair of equal resistors between its input terminal and high output terminal to develop an equal swing voltage on alternate ends of the output resistor when a swing voltage current source is switched between the two input resistors by a control signal. The output is taken from the junction between the output resistor and the low output terminal of the amplifier at the high end of the output resistor.

Abstract: A microprocessor system debug tool has a mainframe which interfaces with a user. A ROM emulator replaces a ROM unit of the microprocessor system to be tested and has a monitor portion which is used to perform debug functions specified by the user. A user defined control line is connected to the interrupt system of the microprocessor system to cause the target microprocessor to stop execution of the user's program and jump to the monitor portion upon the occurrence of a user defined event to execute microprocessor specific debug code generated by the mainframe in response to the user's input. At the conclusion of debug code execution the microprocessor resumes the user's program. A word recognizer is connected to the microprocessor bus to detect the results of the debug code execution, the results being forwarded to the mainframe for display to the user.

Abstract: A logarithmic amplifier calibrator internal to an electronic instrument applies a swept frequency signal via a switch and a single pole resonator to a logarithmic amplifier to be calibrated. The logarithmic amplifier output is digitized and stored as a frequency response for the resonator. The switch is opened and the single pole resonator rings down through the logarithmic amplifier. The ringdown output of the logarithmic amplifier also is digitized and stored as a linear log response. A ripple error look-up table is generated from the linear log response. An approximate bandwidth for the resonator is determined from the frequency response and a ringdown time corresponding to the time the linear log response decreases from the maximum amplitude to a 3 dB down amplitude of the frequency response to determine the exact bandwidth for the resonator.