Abstract: Pixel representations for each of a plurality of superimposed (or splitscreen) display portions are accumulated in a band buffer prior to being transferred to the display. The actual pixel representations are made available to the band buffer from an image memory, with addresses provided by a display list memory. This system minimizes the need for buffering and high speed storage to service the video, by addressing first the display list memory, then in turn using the content of the display list memory to address the image storage, and then in turn using the content of the image storage as the actual pixel representations for accumulation in the band buffer. Two band buffers operate alternatively. The current band buffer is feeding a band of pixel representations to the video shift register while the next band buffer is accumulating the pixel representations of the subsequent video display band. The band buffer accumulates actual pixel representations equivalent to the related band of the display.

Abstract: Simultaneous noncontact testing of voltages across a full line of test sites on an integrated circuit chip-to-test is achieved with high time resolution using photoelectron emission induced by a pulsed laser focussed to a line on the chip-to-test, together with high speed electrostatic deflection perpendicular to the line focus. Photoelectrons produced by the line focus of pulsed laser light are imaged to a line on an array detector, the measured photoelectron intensities at array points along this line representing voltages at corresponding points along the line illuminated by the laser focus. High speed electrostatic deflection applied during the laser pulse, perpendicular to the direction of the line focus, disperses the line image (column) on the array detector across a sequence of sites at right angles (rows), thereby revealing the time-dependence of voltages in the column of test sites with high time resolution (in the picosecond range).

Abstract: A matrix addressable liquid crystal display includes a thin film circuit supported on a substrate having a plurality of parallel bit lines. A plurality of individual pixel circuits each include a two terminal bi-directional gate device which is formed from at least one thin film layer with one gate device terminal connected with the associated bit line. A terminal plate is connected in circuit with the other terminal of the gate device. A transparent cover plate is spaced above the thin film circuit with a transparent conductor structure on the underside of the cover plate.The space beneath the cover plate is filled with a liquid crystal display material to form individual display pixel circuits at the terminal plates. A plurality of parallel word lines are arranged orthogonally to, and insulated from, the bit lines. The word lines are connected in circuit with the individual display pixel circuits at the respective cross-overs with the bit lines.

Abstract: The transistor comprises two electrodes, source (12) and drain (13), with a semiconductor tunnel channel (11) arranged therebetween. A gate (14) for applying control signals is coupled to the channel. The semiconductor, at low temperatures, behaves like an insulator with a low barrier (some meV) through which charge carriers can tunnel under the influence of an applied drain voltage. The tunnel current can be controlled by a gate voltage V.sub.G which modifies the barrier height between source and drain thereby changing the tunnel probability.

Abstract: Covering metal test pads of a passivated integrated circuit process intermediate wafer or completed integrated circuit chip-to-test, with a thin conductive overlayer, and then accessing the test pads through the passivation layer and conductive overlayer, by a pulsed laser to provide voltage-modulated photon-assisted tunneling through the insulation layer, to the conductive overlayer as an electron current, and detecting the resulting electron current, provides a nondestructive test of integrated circuits. The passivation, normally present to protect the integrated circuit, also lowers the threshold for photoelectron emission. The conductive overlayer acts as a photoelectron collector for the detector. A chip-to-test which is properly designed for photon assisted tunneling testing has test sites accessible to laser photons even though passivated.

Abstract: Data compression for transfer (storage or communication) by a continuously adaptive probability decision model, closely approaches the compression entropy limit. Sender and receiver perform symmetrical compression/decompression of binary decision n according to probabilities calculated independently from the transfer sequence of 1 . . . n-1 binary decisions. Sender and receiver dynamically adapt the model probabilities, as a cumulative function of previously presented decisions, for optimal compression/decompression. Adaptive models for sender and receiver are symmetrical, to preserve data identity; transfer optimization is the intent. The source model includes a state generator and an adaptive probability generator, which dynamically modify the coding of decisions according to state, probability and bit signals, and adapt for the next decision.

Abstract: Using as an actuator a stepper motor operated in a position-sensed closed loop mode via an electronic commutator by position and anomaly corrected motion control signals provided by a programmable logic array and by a microprocessor, provides a precision power positioner. The correct enabling of the motor coils, based on position sensing of the motor phase, using electronic commutation for the stepper motor, transforms the problem of enabling coil selection to the programmable logic array, which by its logic provides a simplified operating control as a function of present armature position feedback, and by a microprocessor corrects for anomalies such as temperature rise, square-law, and phase increase as a function of position desired and present armature position feedback signals, and thus provides high positional accuracy, high speed and force (torque) control independent of the motor cardinal step positions.

Abstract: Adaptive training of a system for discrete utterance recognition during continuous speech permits single prototype utterances to be adapted to the needs of the talker, during operation, without tedious multiple recitation for training of prototypes. Initial training of the recognition system is by a single utterance (or simulation) of a prototype vocabulary. Operation proceeds, so long as utterances are recognized, until an unrecognized utterance is detected. The system then prompts a choice of prototype vocabulary keyword candidates, which the talker may then choose and utter. The system calculates three recognition distance values as follows:D1--unrecognized utterance vs. prototype vocabulary keyboard candidateD2--prototype vs. prototype vocabulary keyword candidateD3--prototype vs. unrecognized utterance.

Abstract: A resilient gripper pad stores deformation energy just before the gripped object starts to slip, then rapidly accelerates as it suddenly releases the energy in the springback to rest position. An accelerometer in the resilient pad (corrected for ambient acceleration by differentiation with a nearby second accelerometer) provides information by which the control computer of a closed loop robot system mandates the manipulation of objects by controlled slipping. Controlled transitions of gripping (releasing) action evoked by the control computer provide related sequences of grip (slide) events, with one or more slip (pad chatter) events intervening at the threshold. Prior to the slide, there is an instant when the gripped object starts to slip on a slip pad on one digit of the gripper, but remains frictionally gripped by a resilient pad on the opposing digit. During this instant, the resilient pad deforms downward because of gravity on the gripped object.

Abstract: Equipping a secondary data flow facility with additional capability, to emulate for certain operations the simultaneous processing of the prerequisite instruction and the dependent instruction, significantly improves simultaneous pipeline processing of inherently sequential instructions (k)-at-a-time, by eliminating delays for calculating prerequisite operands. For example, Instruction A+B=Z1 followed by Instruction Z1+C=Z2 is inherently sequential, with A+B=Z1 the prerequisite instruction and Z1+C=Z2 the dependent instruction. The specially equipped secondary data flow facility does not wait for Z1, the apparent input operand from the prerequisite instruction; it simulates Z1 instead, performing A+B+C=Z2 in parallel with A+B=Z1. All data flow facilities need not be fully equipped for all instructions; the secondary data flow facility may be generally less massive than a primary data flow facility, but is more sophisticated in a critical organ, such as the adder.

Abstract: Silicon dioxide insulating films for integrated circuits are provided with enhanced electronic properties, including enhanced dielectric breakdown of MOS insulating layers and reduced trapping of holes by exposing a metal oxide semiconductor wafer including an exposed silicon dioxide layer, in an ambient of flowing oxygen gas, to heating radiation from a halogen lamp for a duration on the order of 100 seconds to achieve annealing temperature on the order of 1000.degree. C.For reduced hole trapping, the ambient gas is oxygen and the annealing temperature is on the order of 1000.degree. C. for a duration on the order of 100 seconds, depending on the oxide thickness.Nitrogen, occurring at the silicon-silicon dioxide interface as a result of previous processing including a long anneal in nitrogen, increases the improvement of the silicon dioxide by the subsequent rapid thermal annealing in oxygen.

Abstract: Silicon dioxide insulating films for integrated circuits are provided with enhanced electronic properties, including decreased water content and reduced trapping of electrons, by exposing a metal oxide semiconductor wafer including an exposed silicon dioxide layer, in an ambient of flowing inert gas, to heating radiation from a halogen lamp for a duration on the order of ten seconds to achieve annealing temperature in the range 600C.-800C.

Abstract: This composite back-etch/lift-off stencil method avoids the uncontrolled changes in the properties of contacts in small devices caused by the close proximity of the lift-off resist stencil to the contact area during the precleaning, surface preparation and metal deposition processes. This method limits the area of the wafer exposed to back-etching and thus restores the freedom of choice of contact metallurgy. Back-etching is only applied in the areas of the wafer near to the contact holes; lift-off techniques are used for the rest of the integrated circuit.

Abstract: In an analog-to-digital converter implemented in logic operating on the multiple lobes of a threshold curve, such as Josephson SQUIDs, two sampling registers are provided with sufficient offset to guarantee stability at sampling in one or the other regardless of other factors. Knowledge of bit value of the next lower bit order position permits determination of which sampling is valid. Encoder logic selects the valid sampling register retroactively.Each sampling register bit order position has two sampling SQUIDs and latching self-gated ANDs. Bias values are provided at higher orders to increment the phase offset so as to ensure low-to-high order readout.The lowest two bit orders may be implemented in simplified logic, effectively giving two bit order positions for logic and SQUIDs equal to that of one higher order bit position.

Abstract: This precision probe uses optical feedback in the X and Y dimensions to locate a microprobe in the airspace over a test pad, and uses pressure feedback in the Z dimension to control Z approach and penetration. The precision probe inspects a target by coarse positioning a guided microprobe to make contact at a selected probe pad. Guidance is optical, by light reflected, from a target by a dual mirror focusing system of concave mirror and flat mirror, to a transducer. Up and down Z positioning of the microprobe is carried out by a shaft positioned by an air diaphragm which is driven to the target by applied air pressure delivered via an air tube, providing the desired penetration of microprobe to microtarget. The probe is retracted by atmospheric pressure.

Abstract: The invention is an all-soliton sampler for accessing very high speed circuits. A soliton is switched in two parallel branches, one including the device-under-test and the other including a programmable delay line implemented in soliton devices. The outputs of these two branches are used as controls to a soliton comparator which, in turn, controls a Josephson detector gate. This circuit permits a relatively slow rise time external trigger pulse to initiate an extremely narrow sampling pulse.

Abstract: Control of pixel configuration, as a function of pixel sequence as well as instantaneous pixel value, permits the use in displays of complex multi-bit pixel configurations with a minimum of optical aberrations.The present pixel configuration is a function of the bit value (low order bit) of the neighbor pixel (previous pixel) as well as of the bit value of the present pixel. Each pixel is controlled by its own two-bit midtone selection value and, in addition, is controlled to the bit value of the low order bit of the previous pixel, according to a truth table.The control circuitry includes a one-pixel interval delay latch which provides the bit value data for the low order bit of the prevous pixel as input to the pixel configurating decoder so that the pixel configurating decoder selects a pixel configuration as a composite function of previous pixel bit value and present pixel bit value.

Abstract: The low temperature electronic package is a right angle connection utilizing an interposer rod between horizontal and vertical substrates. The interposer rod of insulating crystalline substrate material, has a superconducting metal ground plane on its surface, which ground plane is covered by an insulating film. Over the insulating film, the interposer has a number of arcuate conductors to which respective conductors of both the horizontal and vertical substrates are connected at controlled collapse pads for good electrical and mechanical connection. All circuits are effectively transmission lines because the underlying ground plane is continuous.The interposer rod provides a robust, low inductance connector mechanism with a strain minimizing configuration, which permits both horizontal and vertical substrates to interconnect with great connection versatility. It provides for convenient removal and has great resistance to failure related to repeated temperature cycling.

Abstract: One or more monolayers of cerium arrayed on the surface of a niobium metal acts as a catalyst to oxidation of the niobium at ambient temperature and results in a very thin, very high quality insulating layer which may be configured by patterning of the catalyst. Significant amounts of Nb.sub.2 O.sub.5 are formed at pressures as low as 6.6.times.10.sup.-6 Pa, promoted by the presence of the cerium. This catalytic activity is related to the trivalent to tetravalent valence change of the cerium during oxidation. The kinetics of Nb.sub.2 O.sub.5 formation beneath the oxidized cerium shows two stages:the first stage is fast growth limited by ion diffusion;the second stage is slow growth limited by electron tunneling.Other catalytic rare earths usable instead of cerium are terbium and praseodymium; other substrate materials usable instead of niobium are aluminum, hafnium, silicon and tantalum, or oxidizable alloys thereof.

Abstract: Planar junction Josephson interferometer in which the junctions (24) are "buried" underneath the interferometer bridge (27) connecting the junction counter-electrodes (25). The insulation (26) that separates the common base electrode (22) from the bridge (27) is extended between the bridge and the upper surfaces of the counter-electrodes. This design permits, without decreasing the interferometer loop inductance, a reduction of the interferometer area and thus results in a higher packaging density in logic or memory applications.The buried junction concept can be applied in symmetric or asymmetric interferometer designs with virtually any number of junctions, any type of input current control or current feeding scheme.The interferometer can be produced using conventional evaporation, photo-resist, and etch processes based on optical lithography. Further area reduction is achieved in applying e-beam or x-ray technology.