Abstract: According to one embodiment of the present invention, an output buffer (200) includes a first output driver (86) having a gate oxide protected from voltage changes on an output (16). A second output driver (88) also has a gate oxide protected from voltage changes on the output (16). A level shifter (60) includes at least one cascode device (66, 68, 70, 72) and switches the first output driver (86) according to the values of a data input (12) and an enable input (14). A bias-generation circuit (300) generates a quasi-failsafe voltage that is approximately equal to a chip core voltage when a power supply (4) is supplying the chip core voltage and equal to a portion of the chip core voltage when the power supply (4) is not supplying the chip core voltage. The bias-generation circuit (300) is coupled to a first output cascode (80) coupled to the first output driver (86), to a second output cascode (84) coupled to the second output driver (88), or to the cascode device (66, 68, 70, 72) of the level shifter (60).

Abstract: A data processing apparatus includes control circuitry (15, 73) connectable to a peripheral device (17) for performing an access of the peripheral device, and data processing circuitry (13) connected to the control circuitry. The control circuitry includes synchronizing circuitry (29, 77) for synchronizing the control circuitry with the data processing circuitry after completion of the peripheral access.

Abstract: A high frequency clock signal generator (10) is disclosed. The clock signal generator includes a power supply (12, 14), a first resonant tunneling diode (18) coupled to a first terminal of the power supply and an output node (22), and a second resonant tunneling diode (20) coupled to the output node (22) and a second terminal of the power supply. A signal source is coupled to the output node (22) and periodically switches the first and second resonant tunneling diodes (18, 20) between a first state and a second state. The signal source comprises an oscillating signal generator (26) and a transmission line (28) coupled to the output node (22) of the clock signal generator. The oscillating signal generator (26) produces an oscillating input signal, which is reflected by the transmission line (28). The resonant tunneling diode configuration provides rapid voltage swings at the output, thus allowing the generation of a high frequency clock signal of 25 GHz or more.

Abstract: A frontside ground plane (306) integrated circuit with backside contacts (312) plus optional passive components such as microstrip (308) and capacitors. The frontside ground plane provides direct heat dissipation from active junctions such as heterojunction and field effect transistors.

Abstract: A method for maintaining the buffer capacity of a polishing slurry during chemical-mechanical wafer polishing, the method comprising circulating the polishing slurry in a chemical-mechanical wafer polishing apparatus, monitoring the pH of the polishing slurry, combining an agent into the polishing slurry to adjust the pH of the polishing slurry and maintaining the pH of the polishing slurry within a predetermined range, thereby maintaining the buffer capacity of the polishing slurry.

Abstract: In one form of the invention, an emitter structure for a bipolar transistor is disclosed. The structure is comprised of an emitter layer 6 of Al.sub.x Ga.sub.1-x As, where x>0.4, abutting a base layer 8.

Abstract: Method of stress-aligning a thermally sensitive element may comprise the step of forming a thin film layer of thermally sensitive material (80). The thin film layer of thermally sensitive material (80) may be crystallized. A stress alignment layer (82) may be formed in communication with the thin film layer of thermally sensitive material (80). The thin film layer of thermally sensitive material (80) may be heated above a transition temperature of the thermally sensitive material. The stress alignment layer (82) may be expanded relative to the thin film layer of thermally sensitive material (80). The thin film layer of thermally sensitive material (80) may be cooled below the transition temperature of the thermally sensitive material.

Abstract: An ultrawide bandwidth z-axis interconnect which has a z-axis lap joint structure with embedded ground planes that self compensate for the interface misalignment and impedance mismatch. The structure acts as a low pass filter that can be tailored to meet performance requirements from DC to in excess of 100 GHz. The area required for the interface is reduced while increasing the alignment tolerance range. The interconnect structure is easily modeled as a multi-element low pass filter with interfacing transmission lines (microstrip or stripline) to allow for rapid design efforts and reduction in cycle time for a program.

Abstract: Apparatus for optical communications (10, 20, 30, 60 90) includes an optically switched resonant tunneling device (12, 22, 42, 62, 92) being exposed to an input light. The optically switched resonant tunneling device (12, 22, 42, 62, 92) generates a first and second voltage levels in response to the intensity level of the input light. A lasing device (16, 28, 46, 68, 74, 100) is coupled to the optically switched resonant tunneling device (12, 22, 42, 62, 92). The lasing device (16, 28, 46, 68, 74, 100) generates and modulates an output light in response to the first and second voltage levels.

Abstract: According to one embodiment of the present invention, an output buffer (200) includes a first output driver (86) and a second output driver (88). A first output cascode (80) coupled to the first output driver (86) protects the gate oxide of the first output driver (86) from voltage changes on the output (16). A second output cascode (84) coupled to the second output driver (88) protects the gate oxide of the second output driver (88) from voltage changes on the output (16). A level shifter (60) includes multiple cascode devices (66, 68, 70, 72) and switches the first output driver according to the values of a data input (12) and an enable input (14). A first testability device (202, 204, 206, 208) coupled to a cascode device (66, 68, 70, 72) of the level shifter (60) generates a current in response to failure of the cascode device (66, 68, 70, 72).

Abstract: A novel PNP driven NMOS (PDNMOS) protection scheme is provided for advanced nonsilicide/silicide submicron CMOS processes. The emitter of a PNP transistor and the drain of protection NMOS device are connected to an I/O pad for which ESD protection is provided by the PDNMOS. The collector of the PNP transistor and the gate of the protection NMOS transistor are connected to ground through a resistor. The source of the protection NMOS transistor is grounded. The base of the PNP transistor is connected to either a capacitor or the parasitic capacitor of the integrated circuit.

Abstract: A memory system is organized as a matrix including a memory cell at each intersection of a bit line with write and read word lines. Each memory cell comprises a first FET 20 having its gate coupled to a write word line and its drain coupled to a bit line, a second FET 22 having its source coupled to the bit line and its drain coupled to a read word line, and first and second negative resistnce devices 24,26 coupled in series between a supply voltage and a substrate voltage, the common point SN of the series-connected negative resistance devices being coupled to the source of the first FET and to the gate of the second FET. Preferably, the first FET 20 is a p-channel device, the second FET 22 is an n-channel device, and the first and second negative resistance devices 24,26 are RTDs. In a second embodiment, a memory system has a memory cell at each intersection of a bit line with a word line.

Abstract: A fixed optic sensor system (200) comprising a sensor system (210), and electronic sub-system (205) and a communications means (215). The system can be used for detecting the presence of various sample (236) properties and in that regard has widespread application by leveraging off various miniaturized sensor configurations including surface plasmon resonance (50), fluorescence (80), light transmission (125) and others (150). In one embodiment, the communications means (215) is a wireless transmitter/receiver. In another embodiment, a hand held instrument (358) can be used on-site and communicates with the sensor (350) to receive sample (352) related data and transmit it to a remote processing system (370) for further analysis. In yet another embodiment, a hand held instrument (403) has a plurality of cardiac marker binding ligands (400) deposited on the sensor/sample interface providing a medical diagnosis and point-of-care device (403).

Abstract: An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal thereof, which signal path includes a memory circuit (121C, 127C). The memory circuit is coupled to the output terminal and is selectively operable to detect and resolve voltage contention at the output terminal, and is also selectively operable to isolate itself from voltages at the output terminal.

Abstract: A method for fabricating a bipolar transistor comprising the steps of: implanting portions 320 of a semiconductor material structure with ions to render the portions semi-insulating; forming an emitter contact region 332 at an exposed surface of a base layer 308 in a non-implanted portion of the material structure; forming an epitaxial layer of semiconductor material 322 over the exposed surface in an implanted portion of the material structure; and forming a base contact 330 over said epitaxial layer. In accordance with one embodiment of the invention, the method includes the further step of forming a second epitaxial layer of semiconductor material 324 over the first epitaxial layer 322 and then forming the base contact 330 on the second epitaxial layer 324. In accordance with another embodiment, the method includes the further step of forming a second layer of epitaxial material over the exposed surface prior to forming the epitaxial layer of semiconductor material.

Abstract: A circuit and method for implementing a MOSFET gate driver. Two bipolar NPN transistors (Q1, Q2), constructed to achieve rail-to-rail swings when driving a capacitive load (23) by overlapping their respective emitter regions (13) over their contained contact regions (19) to prolong internal device saturation and resulting turn-off delays, alternately connect the gate drive terminal (31) to either a supply terminal (HVDC) or an output terminal (29). Predrive circuitry for these transistors comprises NMOS transistors (M9, M18, M12 and M13). The NPN transistors are supplemented by a CMOS inverter (PMOS transistor M6 and NMOS transistor M17). A PMOS transistor (M7) provides additional base drive for transistor Q1 when the gate drive node is approaching the supply node. A diode (D2) protects transistor Q1 against base-emitter avalanche and protects transistor M7 from excessive drain-to-source voltages.

Abstract: An integrated biochemical sensor (200) for detecting the presence of one or more specific samples (240) having a device platform (355) with a light absorbing upper surface and input/output pins (375) is disclosed. An encapsulating housing (357) provides an optical transmissive enclosure which covers the platform (355) and has a layer of fluorescence chemistry on its outer surface (360). The fluorophore is chosen for its molecular properties in the presence of the sample analyte (240). The detector (370), light sources (365, 367, 407, 409) are all coupled to the platform (355) and encapsulated within the housing (357). A filter (375) element is used to block out unwanted light and increase the detector's (370) ability to resolve wanted emission light.

Abstract: Low-side driver circuit (200) for data transmission applications includes external connection (202) for connecting and providing drive current to an external physical interface circuit. Sink transistor (210) forms an isolation from the physical interface circuit, and channels low-side drive current to external connection (202). Sink transistor (210) includes base (216), collector (208), and emitter (224). Emitter follower transistor (228) associates with sink transistor (210), and in conjunction with "A" input to the gate of transistor (228), sink transistor (210) controls the state of emitter follower transistor (228). Blocking transistor (206) associates with base (216) of sink transistor (210) to block the base of sink transistor (210) in the off state of sink transistor (210). Pull-down diodes (218) and (220) associate with base (216) of sink transistor (210) to pull down the voltage of the base when sink transistor (210) is in an off state.

Abstract: According to the present invention, a system (10) for optimizing the operating characteristics of a CMOS integrated circuit (12) is provided. The integrated circuit has at least one n-channel transistor (18) and at least one p-channel transistor (16) formed on a common substrate. The n-channel transistor (18) and the p-channel transistor (16) each have a threshold voltage which can be adjusted by varying a voltage bias applied to the common substrate. A control means (14) couples to the common substrate. The control means (14) is operable to apply a varying voltage bias to the common substrate in order to reduce leakage current in the integrated circuit (12) in a standby mode and increase performance of the integrated circuit (12) in an active mode.

Abstract: A voltage regulator (10) comprising a vertical channel transistor (12). The vertical channel transistor (12) may have a gate (16), a voltage input terminal (18), and a voltage output terminal (20). A reference voltage supply (14) may be coupled to the gate (16).