Abstract: A size-arrayed emitter structure is disclosed for use in a field emission display device. The emitter structure is designed such that each emitter array (illustratively, an array comprising microtips 40 in a 5.times.5 matrix) has an emitter hole 52 size (critical dimension) distribution that is centered on the optimum hole critical dimension and extends past the point at which the emitter tip 40 will operate. If the manufacturing process varies and produces an actual critical dimension larger than the designed value, emitters with the designed critical dimensions smaller than optimal will shift toward optimal, and emitters with critical dimensions smaller than the minimum operating value will become operational, while emitters with designed critical dimensions larger than optimal will cease to function.

Abstract: The emitter plate 60 of a field emission flat panel display device includes a layer 68 of a resistive material and a mesh-like structure 62 of an electrically conductive material. A conductive plate 78 is also formed on top of resistive coating 68 within the spacing defined by the meshes of conductor 62. Microtip emitters 70; illustratively in the shape of cones, are formed on the upper surface of conductive plate 78. With this configuration, all of the microtip emitters 70 will be at an equal potential by virtue of their electrical connection to conductive plate 78. In one embodiment, a single conductive plate 82 is positioned within each mesh spacing of conductor 80; in another embodiment, four conductive plates 92 are symmetrically positioned within each mesh spacing of conductor 90.

Abstract: An anode plate 50 for use in a field emission flat panel display device comprises a transparent planar substrate 58 having a plurality of electrically conductive, parallel stripes 52 comprising the anode electrode of the device, which are covered by phosphors 54.sub.R, 54.sub.G and 54.sub.B. A substantially opaque, electrically insulating material 56 is affixed to substrate 58 in the spaces between conductors 52, acting as a barrier to the passage of ambient light into and out of the device. The electrical insulating quality of opaque material 56 increases the electrical isolation of conductive stripes 52 from one another, reducing the risk of breakdown due to increased leakage current. Opaque material 56 preferably comprises glass having impurities dispersed therein, wherein the impurities may include one or more organic dyes, selected to provide relatively uniform opacity over the visible range of the electromagnetic spectrum.

Abstract: The emitter plate 60 of a field emission flat panel display device includes a layer 68 of a resistive material and a mesh-like structure 62 of an electrically conductive material. A conductive plate 78 is also formed on top of resistive coating 68 within the spacing defined by the meshes of conductor 62. Microtip emitters 70, illustratively in the shape of cones, are formed on the upper surface of conductive plate 78. With this configuration, all of the microtip emitters 70 will be at an equal potential by virtue of their electrical connection to conductive plate 78. In one embodiment, a single conductive plate 82 is positioned within each mesh spacing of conductor 80; in another embodiment, four conductive plates 92 are symmetrically positioned within each mesh spacing of conductor 90.

Abstract: An anode plate 40 for use in a field emission flat panel display device comprises a transparent planar substrate 42 having a plurality of electrically conductive, parallel stripes 46 comprising the anode electrode of the device, which are covered by phosphors 48.sub.R, 48.sub.G and 48.sub.B, and a gettering material 52 in the interstices of the stripes 46. The gettering material 52 is preferably selected from among zirconium-vanadium-iron and barium. The getter 52 may be thermally reactivated by passing a current through it at selected times, or by electron bombardment from microtips on the emitter substrate. The getter 52 may be formed on a substantially opaque, electrically insulating material 50 affixed to substrate 42 in the spaces formed between conductors 46, which acts as a barrier to the passage of ambient light into and out of the device. Methods of fabricating the getter stripes 52 on the anode plate 40 are disclosed.

Abstract: A size-arrayed emitter structure is disclosed for use in a field emission display device. The emitter structure is designed such that each emitter array (illustratively, an array comprising microtips 40 in a 5.times.5 matrix) has an emitter hole 52 size (critical dimension) distribution that is centered on the optimum hole critical dimension and extends past the point at which the emitter tip 40 will operate. If the manufacturing process varies and produces an actual critical dimension larger than the designed value, emitters with the designed critical dimensions smaller than optimal will shift toward optimal, and emitters with critical dimensions smaller than the minimum operating value will become operational, while emitters with designed critical dimensions larger than optimal will cease to function.

Abstract: The emitter plate 60 of a field emission flat panel display device includes a layer 68 of a resistive material and a mesh-like structure 62 of an electrically conductive material. A conductive plate 78 is also formed on top of resistive coating 68 within the spacing defined by the meshes of conductor 62. Microtip emitters 70, illustratively in the shape of cones, are formed on the upper surface of conductive plate 78. With this configuration, all of the microtip emitters 70 will be at an equal potential by virtue of their electrical connection to conductive plate 78. In one embodiment, a single conductive plate 82 is positioned within each mesh spacing of conductor 80; in another embodiment, four conductive plates 92 are symmetrically positioned within each mesh spacing of conductor 90.

Abstract: A grooved anode plate 40 for use in a field emission flat panel display device comprises a transparent planar substrate 42 having a plurality of electrically conductive, parallel stripes 46 comprising the anode electrode of the device, which are covered by phosphors 48.sub.R, 48.sub.G and 48.sub.B. In one embodiment, grooves 50, having generally straight sidewalls, are formed in the upper surface of planar substrate 42 at the interstices of conductors 46. In a second embodiment, grooves 50', which provide a substantial undercutting of the material of substrate 42' adjacent the edges of conductors 46', are formed in the upper surface of planar substrate 42' at the interstices of conductors 46'. A substantially opaque, electrically insulating material 52 is affixed to substrate 42 in the grooves 50 formed between conductors 46, acting as a barrier to the passage of ambient light into and out of the device.

Abstract: There is provided a packaged semiconductor device having a multi-layered lead frame assembly (38). An integrated circuit chip (12) has an active face (16) with a plurality of bond pads (18) disposed along its center line (14). A first pair of insulating adhesive tape strips (20) adhere a main lead frame (22) to the active face (16) of chip (12). A second pair of insulating adhesive tape strips (28) adhere a respective pair of bus lead frames (30) to the main lead frame (24). Welds (36) electrically interconnect selective leads (22) of main lead frame (22) with respective leads (32) of bus lead frames (30). Tab bonds (40) or wire bonds (42) electrically interconnect selective leads (24) of main lead frame (22) with bond pads (18) on chip (12).

Abstract: A method of forming an array of electron field emitters at a face of a semiconductor layer is disclosed. The method includes the steps of: providing a semiconductor workpiece having a plurality of field emitter sites on a face thereof; for each site, forming a conductive column having a base coupled to the site and an upstanding end opposed to the base; for each conductive column, forming a metallic column on the upstanding end of the conductive column; depositing an electrically conductive polymer layer over the workpiece; etching the electrically conductive polymer layer to selectively expose the metallic columns; placing the workpiece in an electrolytic etchant solution capable of etching the metallic columns; applying an electric potential between the conductive polymer layer and an anode electrode in the etchant to etch the metallic columns into a respective plurality of sharp emitter tips; and removing the conductive polymer layer.

Abstract: An anode plate 40 for use in a field emission flat panel display device comprises a transparent planar substrate 42 having a plurality of electrically conductive, parallel stripes 46 comprising the anode electrode of the device, which are covered by phosphors 48.sub.R, 48.sub.G and 48.sub.B, and a gettering material 52 in the interstices of the stripes 46. The gettering material 52 is preferably selected from among zirconium-vanadium-iron and barium. The getter 52 may be thermally reactivated by passing a current through it at selected times, or by electron bombardment from microtips on the emitter substrate. The getter 52 may be formed on a substantially opaque, electrically insulating material 50 affixed to substrate 42 in the spaces formed between conductors 46, which acts as a barrier to the passage of ambient light into and out of the device. Methods of fabricating the getter stripes 52 on the anode plate 40 are disclosed.

Abstract: A spacer 40 for use in a field emission device includes a comb-like structure having a plurality of elongated filaments 42 joined to a support member 44. The filaments 42, which may be glass, are positioned longitudinally in a single layer between the facing surfaces of the anode structure 10 and the electron emitting: structure 12. Support member 44 is positioned entirely outside the active regions of anode structure 10 and emitting structure 12. Spacer 40 provides voltage isolation between the anode structure 10 and the cathode structure 12, and also provides standoff of the mechanical forces of vacuum within the assembly. In a second embodiment, spacer 50 includes elongated filaments 52 joined at each end to a support member 54 a and 54b, the additional support facilitating handling, fabrication and assembly.

Abstract: Reaction gases are prevented from escaping from a reaction chamber through the use of flexible or gas seals between the interface of the reaction chamber and the junction used to connected successive reaction chambers.

Abstract: A device (10) for controlling current through a circuit has an antifuse material (18) separating a first conductor (12) and a second conductor (20). An insulating element (14) and another insulating element (16) further separate the first conductor (12) from the second conductor (20). The antifuse material (18) includes a dopant which raises the band gap and seals off paths in grain boundaries of the antifuse material (18) in order to limit leakage current from flowing between the first conductor (12) and the second conductor (20). When an interconnection is desired, a high voltage pulse is applied across the first conductor (12) and the second conductor (20) to initially break down the antifuse material (18). The breakdown of the antifuse material (18) causes a filament (22) to form between the first conductor (12) and the second conductor (20). The filament (22) creates a conduction path connecting the first conductor (12) and the second conductor (20) electrically together.

Abstract: A circuit for programming an EEPROM 42 which is used to provide trim adjustment for an integrated circuit (IC). The programming circuit provides the capability of programming the EEPROM 42 indefinitely, employing interfaces which are available even after the IC is packaged and encapsulated. Furthermore, it provides the manufacturer or enduser the capability of disabling the programming function permanently, to thereby prevent any inadvertent modifications of the EEPROM 42 data. The programming circuit includes a one-bit EEPROM 32, a nonvolatile memory element which retains its programmed logic state whether or not it is powered up. EEPROM 32 is set during final probe test by the application of a voltage to a probe pad 30 coupled to its set input terminal. Probe pad 30 is exposed such that it may be contacted by a probe prior to IC encapsulation, but is inaccessible after encapsulation.

Abstract: A switchable, uninterruptible, low-current reference generator with zero off-state current includes a cross-coupled, cascodeal .increment.V.sub.be current reference (70,72,74,76,78) for providing an output current, a current mirror (66,68) coupled in a cascode configuration with the current reference, and a start-up circuit (12) responsive to the absence of the output current for generating a start-up current (I.sub.58) to the current mirror. Start-up current is disabled when output current is restored, and the current mirror bootstraps the output current into regulation. Standby logic (10), comprising FET's configured as CMOS inverters, provides a TTL-compatible, active-low input, and switching FET's (60,80,90,92,94) responsive to the standby logic ensure that the reference generator draws no current in its off state. When the reference generator is turned on, a hysteresis circuit (98,52) coupled to the standby logic (10) increases the input voltage required for turn-off.

Abstract: Apparatus for generating an output signal in response to the change in state of any one of a plurality of input signals. The apparatus includes decoding means for each possible combination of input signals, and by an appropriate arrangement of these decoding means, ensures that any change in input signal status causes an output signal to be generated by the arrangement of decoding means. The decoding means includes first and second arrays 10,12, each comprising a matrix of MOS FET's; the FET's 30.sub.ij of the first array 10 are p-channel devices and the FET's 32.sub.ij of the second array 12 are n-channel devices. The matrix of each array is a paralleled configuration of series-connected branches of FET's functioning as decoders. The branches of each array decode input signal combinations of minimum distance two from one another. Arrays 10 and 12 are interconnected in such a manner that they draw no dc current (other than device leakage current).

Abstract: A programmable divide-by-N or divide-by-N+1/2 circuit is responsive to an input clock signal and to a plurality of binary-coded data signals corresponding to the divisor for providing an output clock signal having a frequency which is the frequency of the input clock signal divided by the value encoded on the data signals. The circuit includes two separate down counters 10, 12--one decrementing on the positive-going edge of the input clock signal and the other decrementing on the negative-going edge of the input clock signal.If the divisor is an integer N, the negative-clocked circuitry 12 is disabled and the positive-clocked circuit 10 counts down from N to 1 continuously. If the divisor is N+1/2, both counter circuits are used. In this case, both counters are preset with the value N, the positive-edge-triggered counter 10 decrements from N to zero while the negative-edge-triggered counter 12 decrements from N to one.

Abstract: A method and structure for a titanium tungsten (TiW)/tungsten local interconnect (136) for cells (100) of semiconductor device includes steps and structure resulting from sputtering a titanium tungsten (TiW) layer (128) on semiconductor structure (100) and then forming a tungsten layer over the TiW layer (128). Then, the method is to pattern a layer of resistive polymer (32) such as photoresist in a predetermined lithographic pattern over the structure (100). This forms the local interconnect (136) from the TiW layer (128). Then, by dry etching, the process removes exposed portions of the tungsten and TiW layers. A wet strip process removes resistive polymer (32) from the semiconductor structure (100) to yield TiW/tungsten interconnect (136) for the semiconductor structure (100). Alternatively a single TiW layer is used in which exposed portions of the TiW layer are removed by a wet etch.

Abstract: A frequency doubler having adaptive biasing includes one shot circuits 10 and 12, which are responsive to particular transitions of an input signal for generating pulsed signals at each such transition. The widths of the pulses are determined by the magnitude of a bias current supplied to the one shot circuits. The pulsed signals of one shot circuits 10 and 12 are combined by OR gate 14 to provide an output signal whose frequency is twice the frequency of the input signal. A low-pass filter 16, coupled to the output signal, produces a signal which is a measure of the average voltage level of the output signal. Voltage-to-current converting FET 18, responsive to the average voltage level of the output signal, supplies bias current to one shots 10 and 12. Comparators 20 and 22 detect when the average voltage level is not within a predetermined range, and enable either up or down counting of digital counter 24.