Abstract: Apparatus for optical communications (10, 110, 210) includes a low-temperature grown photoconductor (12, 140, 220) coupled to at least one resonant tunneling device (14, 120, 130, 230, 240). When exposed to an input light, low-temperature grown photoconductor (10, 110, 210) absorbs photons, which decreases the resistivity, and thus the resistance of the photoconductor. This decrease in resistance causes a decrease in the voltage drop across photoconductor (12, 140, 220), which causes a corresponding increase in the voltage drop across resonant tunneling device (14, 120, 130, 230, 140).

Abstract: A surface plasmon resonance (SPR) sensor includes a transparent base housing 12 and a detachable optical housing 19. Radiation from a radiation source 10, disposed within base housing 12, is polarized by polarizing filter 16 and passes through the interface between base housing 12 and optical housing 19. The polarized radiation 18 is reflected from a mirror 20 onto a SPR layer 22, which is formed on an exterior surface of optical housing 19. Layer 22 comprises a thin layer of a conductive material. Radiation 24 reflected from SPR layer 22 re-enters housing 19 and strikes an array 28 of photodetectors. From the intensity of radiation at each photodetector, one can determine the index of refraction of the substance on the opposite side of SPR layer 22.

Abstract: A metal-oxide-semiconductor digital-to-analog converter unit includes a multiplicity of current mirror components 20 in a symmetric array, a resistance network activated by voltage sources providing weighted biasing potentials for the current mirror components, and an electrical coupling of the current mirror components to compensate for variations physical properties across converter unit substrate area. The current mirror components 20 include a current steering portion 21.sub.0 -21.sub.N-1 and 25.sub.0 -25.sub.N-1 coupled to an annular bias transistor 22. The resulting digital-to-analog converter has improved performance characteristics when compared to previously implemented digital-to-analog converter units.

Abstract: This is a method of forming a conductor 26 on an interlevel dielectric layer 12 which is over an electronic microcircuit substrate 10, and the structure produced thereby. The method utilizes: forming an intralevel dielectric layer 14 over the interlevel dielectric layer 12; forming a conductor groove in the intralevel dielectric layer 14 exposing a portion of the interlevel dielectric layer 12; anisotropically depositing a selective deposition initiator 24 onto the intralevel dielectric layer 14 and onto the exposed portion of the interlevel dielectric layer 14; and selectively depositing conductor metal 26 to fill the groove to at least half-full. The selective deposition initiator 24 may selected from the group consisting of tungsten, titanium, paladium, platinum, copper, aluminum, and combinations thereof. In one embodiment, the selective deposition initiator 24 is paladium, and the selectively deposited conductor metal 26 is principally copper.

Abstract: A memory system is organized as a matrix including a memory cell at each intersection of a bit line with write and read word lines Each memory cell comprises a first FET 20 having its gate coupled to a write word line and its drain coupled to a bit line, a second FET 22 having its source coupled to the bit line and its drain coupled to a read word line, and first and second negative resistance devices 24,26 coupled in series between a supply voltage and a substrate voltage, the common point SN of the series-connected negative resistance devices being coupled to the source of the first PET and to the gate of the second FET. Preferably, the first FET 20 is a p-channel device, the second FET 22 is an n-channel device, and the first and second negative resistance devices 24,26 are RTDs. In a second embodiment, a memory system has a memory cell at each intersection of a bit line with a word line.

Abstract: A grooved anode plate 40 for use in a field emission flat panel display device comprises a transparent planar substrate 42 having a plurality of electrically conductive, parallel stripes 46 comprising the anode electrode of the device, which are covered by phosphors 48.sub.R, 48.sub.G and 48.sub.B. In one embodiment, grooves 50, having generally straight sidewalls, are formed in the upper surface of planar substrate 42 at the interstices of conductors 46. In a second embodiment, grooves 50', which provide a substantial undercutting of the material of substrate 42' adjacent the edges of conductors 46', are formed in the upper surface of planar substrate 42' at the interstices of conductors 46'. A substantially opaque, electrically insulating material 52 is affixed to substrate 42 in the grooves 50 formed between conductors 46, acting as a barrier to the passage of ambient light into and out of the device.

Abstract: A method is provided for producing an n-type or p-type epitaxial layer using a doped substrate material. The method includes growing a substrate (12), preferably from a material to which an epitaxial layer can be lattice-matched. The substrate (12) is doped with a predetermined concentration of dopant (14). Preferably, the dopant (14) possesses the ability to rapidly diffuse through a material. An epitaxial layer (16) is grown upon the doped substrate (12). The epitaxial layer (16) and the doped substrate are annealed, thereby causing the dopant (14) to diffuse from the substrate (14) into the epitaxial layer (16).

Abstract: Input and output boundary scan cells respectively include latchable input and output buffers (103,40) which respectively utilize the input and output buffers of the integrated circuit in which the boundary scan cells are provided. The latchable input and output buffers provide the input and output boundary scan cells with a low overhead latching function.

Abstract: A resettable latched voltage comparator includes a resonant tunneling diode 10 connected in series with an amplifier 14 and a power source 16, and a reset circuit 12 connected between a circuit output terminal 18 and a second power source 20. Amplifier 14 converts the value of the voltage at an input terminal 22 into a proportional current at terminal 24; diode 10 detects the condition when the current at terminal 24 rises above a specific value equal to the resonant peak current of resonant tunneling diode 10; and reset circuit 12 controllably forces the voltage at terminal 18 of the circuit to a value approximately equal to the output voltage of power source 16 at terminal 29, thereby reducing the bias across diode 10 to approximately zero. A flash analog-to-digital converter configuration includes a plurality of comparators 200.sub.i having their reference voltage inputs biased from a series-connected chain of resistors 210.sub.i. The input terminals 22.sub.

Abstract: The present invention provides a high efficiency ESD circuit that requires less space through uniform activation of multiple emitter fingers of a transistor structure containing an integral Zener diode. The Zener diode is able to lower the protection circuit trigger threshold from around 18 volts to around 7 volts. This method minimizes series impedance of the signal path, thereby rendering an NPN structure that is particularly well suited for protecting bipolar and CMOS input and output buffers. The ESD circuit of the present invention provides a relatively low shunt capacitance (typically <0.5 pF) and series resistance (typically <0.5 ohm) that are desirable for input and output circuits of present and future contemplated generations of sub-micron bipolar/BiCMOS circuit processes.

Abstract: An integrated circuit includes functional circuitry for performing normal operating functions of the integrated circuit, an output terminal which is accessible externally of the integrated circuit, and an output drive circuit (OB,OA) for receiving an output signal from the functional circuitry and driving the output signal to the output terminal. A switch (TG1,S1) is provided for selectively isolating the output terminal from the functional circuitry, and the switch is connected between the functional circuitry and the output drive circuit.

Abstract: An emulation device (11) distributes common control information (8801) to each of a plurality of clock domains (1213, 1215, 1217) into which the emulation device is partitioned, and also provides the clock domains with individualized clock control (8905, 8907, 8913).

Abstract: An electronic switch (80) having a transistor (T) and a diode (D) formed on a substrate (82) is provided. The electronic switch (80) includes a common transistor collector and diode cathode region (81) of a first conductivity type formed in the substrate (82). The switch (80) also includes a transistor base region (83) of a second conductivity type formed in a first section of the collector region (81) and a transistor emitter region (84) of the first conductivity type formed in a section of the base region (83). Additionally, the electronic switch (80) includes a diode anode region (85) formed of the second conductivity type and in a second section of the collector region (81). At least a portion of the anode region (85) is selectively doped with a metallic dopant to provide centers for charge carrier recombination so as to decrease the recovery time of the diode (D).

Abstract: A voltage regulator (10) is provided. A first bipolar transistor (24) has an emitter connected to a first node (NODE 6) and a base connected to a second node (NODE 5). A second bipolar transistor (30) is scaled N:1 with respect to the first bipolar transistor (24), N greater than one. The second bipolar transistor (30) has an emitter, a base, and a lateral collector. The base is connected to the second node (NODE 5). A first resistor (20) is connected between the first node (NODE 6) and an output node (NODE 2). A second resistor (32) is connected between the first node (NODE 6) and the emitter of the second bipolar transistor (30), and a third resistor (22) is connected between the first node (NODE 6) and a ground node (GND). A current sensing amplifier (12, 14, 34, 38 and 40) has a first input node (NODE 7) connected to the lateral collector of the first bipolar transistor (24) and a second input node (NODE 8) connected to the lateral collector of the second bipolar transistor (30).

Abstract: A method for producing a porous film on a silicon substrate is described. The substrate 14 is placed in a vacuum chamber in the presence of oxygen at specified pressure and temperature for a period of time to form a thin oxide film 10 thereon. Then the conditions in the chamber are altered so that voids 14 of a desired dimension are formed in the oxide film 10. Alternatively, a substrate 20 is subjected to specific conditions in the vacuum chamber whereat oxide islands 22 nucleate on the surface. As the islands grow, they eventually cover most of the surface leaving voids 24 of the desired size.

Abstract: An FED display (10) is provided which is formed from flexible materials. The flexible FED display (10) includes an anode element (12) having a face sheet layer (18) formed from a first layer of flexible insulating substrate material. A cathode element (14) is attached to the anode element (12). The cathode element (14) includes a backing sheet layer (26) formed from a second layer of flexible insulating substrate material (40).

Abstract: An accurate, low-current integrated circuit comparator includes a differential input stage 10 comprising differential pair transistors 22 and 24, differential pair current mirror transistors 26 and 28, and a constant current source transistor 30. The comparator also includes an hysteresis stage 12 coupled to one of the current mirror transistors; the hysteresis stage comprises an hysteresis mirror transistor 34 and a switching transistor 36. The comparator additionally includes a gain stage 14 comprising a gain transistor 38 and a constant current source transistor 40. Finally, the comparator includes an output stage 15 comprising gain transistor 42 in an open-drain configuration. In the disclosed embodiment, the descending trip threshold is set entirely by the ratios of device geometries, and is therefore very accurate and is independent of temperature, lithography and processing variations.

Abstract: A switch mode regulator circuit is provided to facilitate the conversion from one voltage level to another in a substantially power lossless manner. The circuit is particularly advantageous in instances where the power supply can be operable in a discontinuous mode, as inductor-capacitor oscillatory transients ("ringing"), along with its associated voltage spikes at the associated output transistor source, can be avoided. Such transients and their associated voltages are avoided by clamping the gate-source voltage on the circuit's output NMOS transistor over the entire positive operation voltage range.

Abstract: This is a method of fabricating a bipolar transistor on a wafer. The method can comprise: forming a doped emitter contact layer 31 on a substrate 30; forming a doped emitter layer 32 on top of the emitter contact layer, the emitter layer doped same conductivity type as the emitter contact layer; forming a doped base epilayer 34 on top of the emitter layer, the base epilayer doped conductivity type opposite of the emitter layer; forming a doped collector epilayer 36, the collector epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming an collector contact 38 on top of the collector layer; forming a base contact 40 on top of the base layer; forming a emitter contact 44 on top of the emitter contact layer; and selective etching the emitter layer to produce an undercut 45 beneath the base layer.

Abstract: An emitter structure 12 for use in a field emission display device comprises a ballast layer 17 overlying an electrically conductive coating 16 (cathode electrode), which is itself formed on an electrically insulating substrate 18. A gate electrode comprises a coating of an electrically conductive material 22 which is deposited on an insulating layer 20. Cone-shaped microtips 14 formed within apertures 34 through conductive layer 22 and insulating layer 20. In the present invention, insulating layer 20 comprises a dielectric material capable of desorbing at least ten atomic percent hydrogen, which may illustratively comprise hydrogen silsesquioxane (HSQ). HSQ is an abundant source of hydrogen which keeps deleterious oxides from forming on microtip emitters 14. HSQ also reduces the capacitance formed by cathode electrode 16 and gate electrode 22, since its relative dielectric constant is less than 3.5.