Abstract: A design tool for generating design views of a semiconductor chip is presented. The design tool includes an input module, a generation module, a first synthesis module, a user interface module and an extraction module. The input module may be configured to receive input including physical and logical resources and a custom chip specification. The generation module may be configured to generate Register Transfer Level (RTL) views for the semiconductor chip. The first synthesis module may be configured to perform logic synthesis using the RTL views. The user interface module may be configured to query a user whether re-usable intellectual property (IP) is to be generated. The extraction module may be configured to extract and package design information for the re-usable IP in response to a request from the user.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal oscillating at a first frequency in response to (i) a first control signal, and (ii) a second control signal. The second circuit may be configured to generate the second control signal in response to (i) an input signal having a voltage and (ii) the output signal. The second circuit may be configured to compare a peak voltage of the output signal to the input voltage.

Abstract: A method for producing a chip is disclosed. A first step of the method may involve first fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. A second step of the method may be to design a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the cells to form an electrostatic discharge clamp at a power domain crossing. A third step may include second fabricating the chip to add the upper metal layers.

Abstract: A circuit comprising a plurality of first line buffers, an arbiter and a cache. The plurality of first line buffers may be configured to communicate on a plurality of first busses. The arbiter may be configured to perform an arbitration among the first line buffers. The cache block may be configured to (i) determine a particular policy of a plurality of policies in response to a first transaction request from one of the first line buffers winning the arbitration and (ii) generate a second transaction request based upon the first transaction request and the particular policy.

Abstract: An apparatus comprising a plurality of first counters, a second counter, and a logic circuit. The plurality of first counters may each be configured to increment a first value in response to receiving one of a plurality of incoming data packets on an associated port. The second counter may be configured to increment a second value in response to a highest value of said first values being incremented. The logic circuit may be configured to generate an output representing a volume of packet traffic in response to the plurality of first values and the second value. The output signal generally indicates which of a plurality of ports is best suited for implementing flow control.

Abstract: A method for processing an input signal is disclosed. The method generally includes the steps of (A) extracting a compressed signal and a first checksum from the input signal, (B) generating a decompressed signal by decompressing the compressed signal, (C) calculating a second checksum for the decompressed signal and (D) generating a result by comparing the first checksum to the second checksum.

Abstract: A method for calibrating read data strobe gating including the steps of: (A) performing a coarse timing adjustment configured to determine a coarse delay setting that produces invalid data, (B) performing a medium timing adjustment configured to adjust a medium delay setting and the coarse delay setting until valid data is detected, (C) performing a fine timing adjustment configured to adjust the medium delay setting and a fine delay setting until valid data is detected and (D) adding one-half cycle to a gating delay determined by the coarse, the medium and the fine delay settings.

Abstract: A method for floorplan visualization comprising the steps of (A) receiving design information for an integrated circuit design comprising one or more subsystems, (B) generating one or more gate count estimates for the one or more subsystems of the integrated circuit design, (C) generating one or more gate density estimates for gates of the one or more subsystems mapped to one or more programmable areas of a programmable platform device and (D) generating a visual representation of one or more area estimations for each of the one or more subsystems based on the one or more gate count estimates and the one or more gate density estimates.

Abstract: An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the first storage device. The second storage device may be configured to store a second pixel from a second field of the frame of the image at a second physical address in the second storage device. The first and second physical addresses may have the same relative position in an address space of the respective storage devices.

Abstract: An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the first storage device. The second storage device may be configured to store a second pixel from a second field of the frame of the image at a second physical address in the second storage device. The first and second physical addresses may have the same relative position in an address space of the respective storage devices.

Abstract: A method for implementing a circuit design is disclosed. The method generally includes the steps of identifying, replacing and routing. The first step may identify a first cell of the circuit design having (i) a function and (ii) an input pin connectable to one of a first power rail and a second power rail having a different voltage than the first power rail. The second step may replace the first cell with a second cell having (i) the function, (ii) the input pin and (iii) at least one blocking characteristic that reserves (a) a first route completely within a particular conductive layer of the cell between the input pin and the first power rail and (b) a second route completely within the particular conductive layer between the input pin and the second power rail. The third step may route the circuit design incorporating the second cell such that the input pin is connected to one of (i) the first power rail using the first route and (ii) the second power rail using the second route.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: A method for performing motion estimation comprising the steps of (a) determining one or more first vectors representative of a displacement of a first block of a first image in a second image and (b) determining one or more second vectors representative of a displacement of the first block in the second image and a first sub-block and second sub-block of the first block based upon the one or more first vectors, a plurality of error scores, and a combination of the plurality of error scores.

Abstract: A method and apparatus for deinterlacing a picture is disclosed. The method generally includes the steps of (A) calculating a plurality of differences among a plurality of current samples from a current field of the picture, the differences being calculated along a plurality of line segments at a plurality of angles proximate a particular position between two field lines from the current filed, (B) generating a first sample at the particular position by vertical filtering the current field in response to the differences indicating that the particular position is a non-edge position in the picture and (C) generating a second sample at the particular position by directional filtering the current field in response to the differences indicating that the particular position is an edge position in the picture.

Abstract: A grooming switch comprises plural input ports for receiving multi-time-slot input signals and plural output ports for forwarding multi-time-slot output signals. At least five switching stages alternate between time switching and space switching. The first stage is connected to the input ports, and the last stage is connected to the output ports. Each intermediate stage is connected to two other stages. Collectively, these stages perform compact superconcentration of the input signals, copying and distribution of the compact superconcentrated signals, and unicast switching of the distributed signals to form the output signals, resulting in a grooming switch that is rearrangeably non-blocking for arbitrary multicast traffic.

Abstract: The invention may relate to a digital frequency adjuster for adjusting a first frequency of a first signal. The digital frequency adjuster may comprise a first digital delay line and a first control circuit. The first digital delay line may comprise a plurality of taps. The first digital delay line may be configured to (i) receive the first signal and (ii) generate a second signal. The first control circuit may be configured to control dynamic assertion of respective ones of the taps at a rate such that the second signal has a second frequency different from the first frequency of the first signal.

Abstract: A circuit generally including a control function and a checksum function is disclosed. The control function may be configured to assert (i) a start signal in response to a signal having a predetermined sequence of values matching an entry value and (ii) a stop signal in response to the signal matching an exit value. The checksum function may be configured to (i) generate a checksum value for the signal between assertions of the start signal and the stop signal and (ii) generate a result signal in response to comparing the checksum value with an expected value.

Abstract: An apparatus comprising a clock generation circuit, a detect circuit and a select circuit. The clock generator circuit may be configured to generate an output clock signal in response to a control signal. The detect circuit may be configured to generate a detect signal in response to (i) the output clock signal and (ii) an input signal. The select circuit may be configured to generate the control signal by selecting (i) a first input when in a first mode (ii) the detect signal when in a second mode. The first and second modes are selected in response to a selection signal.

Abstract: A system and method are disclosed for reading a multilevel signal from an optical disc. The method includes reading a raw analog data signal from a disc using an optical detector and adjusting the amplitude of the raw analog data signal. A timing signal is recovered from the amplitude adjusted analog data signal and correction is made for amplitude modulation of the raw analog data signal by processing the raw analog data signal and the timing signal.

Abstract: A method of operating a modem generally comprising the steps of (A) transmitting an invalid signal from the modem at each of a plurality of settings for an echo cancelling hybrid of the modem, (B) calculating a plurality of merit values each in response to an echo signal received by the modem in response to the invalid signal, and (C) adjusting the echo cancelling hybrid to a particular setting of the settings determined from the merit values.