Abstract: Techniques of designing a digital phase lock loop are disclosed. In one embodiment, the digital phase lock loop comprises a synchronization unit producing a producing a plurality of clock signals in accordance with a seed clock signal having a frequency, each of the clock signals having a modified frequency over the frequency of the seed clock signal and a phase shift from each other; a phase-frequency detection unit receiving an input signal and a feedback signal, and sampling the input signal and the feedback signal in accordance with the clock signals to determine differences in phase and frequency between the input signal and the feedback signal; a digital control oscillator receiving the clock signals and producing an output signal in reference to the differences from phase-frequency detection unit, and subsequently, a digitally controlled clock signal is produced.

Abstract: An apparatus for memory error control coding comprising a first circuit and a second circuit. The first circuit may be configured to generate a multi-bit digital syndrome signal in response to a read data signal and a read parity signal. The second circuit may be configured to (i) detect an error when the bits of the syndrome signal are not all the same state and (ii) generate an error location signal in response the syndrome signal. The error location signal may be generated in response to fewer than all of the bits of the syndrome signal.

Abstract: A circuit generally comprising a command buffer and a read buffer is disclosed. The command buffer may be configured to (i) buffer a plurality of read commands received by the circuit, wherein each read command has one of a plurality of port values and one of a plurality of identification values and (ii) transmit a tag signal from the circuit in response to servicing a particular read command of the read commands. The tag signal may have a particular port value of the port values and a particular identification value of the identification values as determined by the particular read command. The read buffer may be configured to transmit a read signal within a plurality of first transfers from the circuit in response to servicing the particular read command.

Abstract: An apparatus comprising (i) a first circuit configured to generate one or more node signals at one or more internal nodes and (ii) a second circuit configured to present one or more of the node signals and a trigger signal in response to one or more control signals.

Abstract: An apparatus generally having a plurality of disk drives and a controller is disclosed. Each of the disk drives may have a first region and a second region. The first regions may have a performance parameter faster than the second regions. The controller may be configured to (i) write a plurality of data items in the first regions and (ii) write a plurality of fault tolerance items for the data items in the second regions.

Abstract: An apparatus comprising an audio/video decoder and a storage device. The audio/video decoder may be configured to receive (i) one or more uncompressed audio signals and (ii) one or more compressed audio/video signals. The uncompressed audio signals may be tagged to the compressed audio/video signals and (ii) any of the one or more uncompressed audio signals and the one or more tagged compressed audio/video signals may be stored in the storage device and available for a playback relative to the tags.

Abstract: An apparatus generally having a circuit board and a first strain gauge is disclosed. The circuit board may have a plurality of insulating layers. The first strain gauge may be disposed between two of the insulating layers.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to calculate and present an output signal having a first resolution in response to (i) an input signal having a second resolution and (ii) one or more control signals. The second circuit may be configured to generate the control signals in response to (i) a previous calculation by the first circuit and (ii) one or more input parameters. The first circuit may be configured to scale and filter the input signal.

Abstract: Systems and methods are disclosed for controlling a display device having a display scan line rate by storing incoming data in a buffer, the buffer having a usage level measure; comparing the usage level to the display scan line rate; and adjusting a width of a display scan line to avoid buffer overflow or underflow. The system avoids a costly external frame buffer and automatically handles uncertainties such as jitter in input and output clocks when the system operates in different environments.

Abstract: Systems and methods for controlling a display device include receiving a source video signal from a video source; storing video pixels in one or more line buffers; enhancing the video signal on the fly using data stored in the line buffers; if image enhancement is not necessary, rendering the source video signal and otherwise rendering the enhanced video signal.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate an upconverted signal in response to an input signal and a first oscillation signal. The second circuit may be configured to generate a downconverted signal in response to the upconverted signal and as second oscillation signal. The third circuit may be configured to generate an output signal in response to the downconverted signal and a third oscillation signal derived from the second oscillation signal. The upconverting and downconverting may filter undesired channels from the output signal.

Abstract: An apparatus comprising a first transistor pair, second transistor pair, a third transistor pair and a fourth transistor pair. The first transistor pair may be (i) implemented as thin oxide devices and (ii) configured to receive a differential input signal. The second transistor pair may be (i) implemented as thick oxide devices and (ii) configured to generate a differential output signal in response to the differential input signal. The output signal has a voltage higher than the input signal. The third transistor pair may be (i) connected between the first and second transistor pairs and (ii) configured to protect the first transistor pair. The fourth transistor pair may be (i) connected between the third transistor pair and a ground and (ii) configured to increase an operating speed of the apparatus.

Abstract: The present invention is a computer-based system for managing projects. It allows the user to input data concerning a project and associate individuals with the project. The system then determines a deadline for completing a task associated with the project and send out reminders accordingly. The system provides the user a number of options not available on the conventional docketing systems, such as automatically increasing the frequency with which reminders are sent as the deadline approaches, and automatically increasing the number of individuals to whom the reminders are sent as the deadline draws near.

Abstract: A method for generating a modified view of a circuit layout. In a first step, the method includes receiving the circuit layout from a design rule clean database. In a second step, the method includes extracting a base wafer layout from the circuit layout according to a set of computer executable instructions. In a third step, the method includes modifying the base wafer layout according to the set of computer executable instructions.

Abstract: An apparatus comprising a first control circuit, a second control circuit, a latch circuit and a flip-flop. The first control circuit may be configured to generate a first control signal in response to (i) an input signal from a fuse and (ii) one or more read signals. The latch circuit may be configured to change status in response to the first control signal. The second control circuit may be configured to change the state of the latch circuit in response to (i) one or more read signals and (ii) one or more set signals. The flip-flop may be configured to capture the state of the fuse in response to changing the state of the latch circuit with the first control circuit or the second control circuit.

Abstract: A bus that may be used in an integrated circuit chip. The bus generally comprises a master interface, a slave interface, and a control logic. The master interface may be configured to (i) receive an early command signal having a predetermined timing relationship to a first clock edge and (ii) present a bus wait signal proximate a second clock edge. The slave interface may be configured to (i) present a command signal a delay after the first clock edge and (ii) receive a slave wait signal. The control logic may be configured to (i) register the early command signal to generate the command signal and (ii) convert the slave wait signal into the bus wait signal.

Abstract: A circuit generally comprising a plurality of read input registers, a read output register, a write input register and a plurality of write output registers is generally disclosed. The read input registers may be configured to buffer a first read signal received within a plurality of first transfers. The read output register may be configured to transmit the first read signal in a second transfer. The write input register may be configured to buffer a first write signal received in a third transfer. The write output registers may be configured to transmit the first write signal within a plurality of fourth transfers.

Abstract: A method for re-using diffused cell-based IP blocks in a structured application specific integrated circuit comprising the steps of (A) implementing one or more blocks of intellectual property (IP) using a plurality of cell-based building blocks and (B) providing one or more alternative views for at least one of the one or more blocks of intellectual property.

Abstract: A method for generating a plurality of timing constraints for a circuit design is disclosed. The method generally includes the steps of (A) identifying a plurality of clock signals by analyzing the circuit design, (B) determining a plurality of relationships among the clock signals and (C) generating the timing constraints for the circuit design in response to the clock signals and the relationships.

Abstract: The present invention may provide a circuit generally having a plurality of addressable memory cells and an access control circuit. The access control circuit may be configured to intercept an access to a faulty cell of the plurality of addressable memory cells. The access control circuit may be further configured to redirect the access to a spare cell of the plurality of addressable memory cells.