Abstract: Winged via structures to increase overlay margin are generally described. In one example, a method comprises depositing a sacrificial layer to an interlayer dielectric, the interlayer dielectric being coupled with a semiconductor substrate, forming at least one trench structure in the sacrificial layer wherein the trench structure comprises a first direction along a length of the trench structure and a second direction along a width of the trench structure wherein the second direction is substantially perpendicular to the first direction, depositing a light sensitive material to the trench structure and the sacrificial layer, and patterning at least one winged via structure in the light sensitive material to overlay the trench structure wherein the winged via structure extends in the second direction beyond the width of the trench structure onto the sacrificial layer.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a cavity that extends at least about one micron or greater below the surface of the semiconductor material, filling the cavity with a sacrificial material, forming a dielectric material over the sacrificial material and over at least a portion of the surface of the semiconductor material, and removing a portion of the dielectric material to form an opening to expose a portion of the sacrificial material, wherein the opening has a width that is substantially less than a width of the cavity and the dielectric material is rigid or substantially rigid. The method further includes removing the sacrificial material. Other embodiments are described and claimed.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least a portion of the dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material. Other embodiments are described and claimed.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a capacitor embedded in a dielectric material below the surface of a semiconductor substrate is disclosed. Other embodiments are described and claimed.

Abstract: A method includes depositing a sacrificial gate electrode to one or more multi-gate fins. The sacrificial gate electrode is patterned such that it is coupled to a gate region and substantially no sacrificial gate electrode is coupled to source and drain regions. A dielectric film is formed that is coupled to the source and drain regions. The sacrificial gate electrode is removed and a spacer gate dielectric is deposited to the gate region wherein substantially no spacer gate dielectric is deposited to the source and drain regions. The spacer gate dielectric is etched to completely remove the spacer gate dielectric from the gate region area that is to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric that is to be coupled with the final gate electrode that remains coupled with the dielectric film.

Abstract: A semiconductor device having reduced input capacitance is disclosed. The semiconductor device includes a pedestal region having a gate overlying a sidewall of the pedestal region and gate interconnect overlying a major surface of the pedestal region. The pedestal region includes a conductive shield layer (260). The conductive shield layer (260) is isolated from the gate of the transistor by more than one dielectric layer (330, 340, and 350) to reduce input capacitance. The pedestal region includes an air gap region (1525) to further lower the dielectric constant of the pedestal region between the gate/gate interconnect and the conductive shield layer (260).

Abstract: Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed, a dielectric material coupled with the source region and the drain region of the multi-gate fin, and the subsequent gate structure coupled to the gate region of the multi-gate fin.

Abstract: A device and method for canceling one or more self-jammer signals in a radio-frequency identification system.

Abstract: In a communications packet directed to multiple addresses and having a directory of the addresses in order of transmission, a device receiving the packet may use the directory to help determine when the last frame in which the device has an interest is received, and then enter a low power mode for the remainder of the packet reception. The device constructing the packet for transmission may arrange the frames in a manner that promotes overall power savings in the group of addressed devices.

Abstract: A semiconductor device is formed having lower gate to drain capacitance. A trench (80) is formed adjacent to a drain (20) of the semiconductor device. Trench (80) has a sidewall surface (100) and a surface (90). A doped region (110) is implanted through the sidewall surface (100) of trench (80). A dielectric layer (150) overlies the sidewall surface (100) of trench (80). A shield layer (170) overlies the dielectric layer (150). The shield layer (170) is between a portion of drain (20) and a portion of the gate and gate interconnect of the semiconductor device thereby reducing gate to drain capacitance. The shield layer (170) overlies a minority portion of the surface (90) of trench (80). A second shield layer (270) further reduces gate to drain capacitance.

Abstract: A semiconductor device is formed having a pedestal. The pedestal includes at least two dielectric layers. The pedestal has a sidewall and a major surface. A conductive layer is formed overlying the pedestal. A vertical portion of the conductive layer adjacent to the sidewall of the pedestal is a gate of the transistor. The portion of the conductive layer overlying the major surface can be used as interconnect. The gate and gate interconnect are contiguous and formed in a single process. A conductive shield layer may be integrated into the pedestal. The conductive shield layer functions as a faraday shield that reduces gate to drain capacitance of the device.

Abstract: In accordance with one or more embodiments, a semiconductor structure includes a semiconductor substrate, a first semiconductor material over the semiconductor substrate, and a second semiconductor material over a portion the first semiconductor material, wherein the second semiconductor material comprises silicon-germanium-carbon (SiGeC) and wherein the first semiconductor material is a silicon epitaxial layer. The semiconductor structure further includes an active device, wherein a portion of the active device is formed in the second semiconductor material and a dielectric structure extending from the first surface of the first semiconductor material into the semiconductor substrate through the first semiconductor material.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material using an electrochemical etch to form a first cavity, a second cavity, wherein the first cavity is isolated from the second cavity, a first protrusion is between the first cavity and the second cavity, and the semiconductor material comprises silicon. The method further includes performing a thermal oxidation to convert a portion of the silicon of the semiconductor material to silicon dioxide and forming a first dielectric material over the first cavity, over the second cavity, over at least a portion of the semiconductor material, and over at least a portion of the first protrusion. Other embodiments are described and claimed.

Abstract: Briefly, in accordance with one or more embodiments, a method and device capable of canceling self-jammer and one or more other interfering signals in an radio frequency identification system or the like is disclosed.

Abstract: Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.

Abstract: Stationary wireless network stations are woken up using Wake-on-WLAN functionality. Wake-on-WLAN is provided by paging stations in a wireless network. Paging may support mobile stations across multiple access points. Paging may also support stationary nodes with reduced overhead. Wake-on-WLAN is also provided to stationary stations in idle mode by signifying a wake-on event in a traffic indication map (TIM). Wake-on events may occur when a station is associated or disassociated with an access point. Upon receiving a wake-on event, a station associates or reassociates with an AP if necessary.

Abstract: Briefly, in accordance with one or more embodiments, an appliance having a camera and camera window may include a shutter puck slidably disposed in a slot in which the camera window may be disposed. The puck may have a wiper pad that is capable of cleaning the camera window as the puck is slid within the slot from a camera on to a camera off or privacy position. The puck may comprise an at least partially deformable material so that the puck may be inserted into and/or removed from the slot by at least partially deforming the puck to allow the puck to be installed in or extracted from the slot. The puck may further include a grip rib structure or the like to allow a user to grasp the puck and slide the puck within the slot.

Abstract: Inductors using bulk metallic glass (BMG) material and associated methods are generally described. In one example, an apparatus includes an electrically conductive core material, an electrically insulative material coupled with the electrically conductive core material, and a magnetic bulk metallic glass (BMG) material coupled with the electrically insulative material, wherein the electrically conductive core material, the electrically insulative material, and the magnetic BMG material form an inductor.

Abstract: Briefly, in accordance with one or more embodiments, a dielectric platform is at least partially formed in a semiconductor substrate and extending at least partially below a surface of a semiconductor substrate. The dielectric platform may include structural pillars formed by backfilling a first plurality of cavities etched in the substrate, and a second plurality of cavities formed by etching away sacrificial pillars disposed between the structural pillars. The second plurality of cavities may be capped to hermetically seal the second plurality of cavities to impart the dielectric constant of the material contained therein, for example air, to the characteristic dielectric constant of the dielectric platform. Alternatively, the second plurality of cavities may be backfilled with a material having a lower dielectric constant than the substrate, for example silicon dioxide where the substrate comprises silicon.

Abstract: Techniques are described that can be used to maximize the interference suppression capability of space-time coded systems by managing synchronous transmission signaling. To enhance the probability of the occurrence synchronous interference and accordingly increase interference cancellation capability at a receiver, a network of at least two transmitters in a network may utilize similar structured coding schemes and coordinate transmission so that the receiver receives co-channel signals synchronously.