Patents Represented by Attorney Cool Patent, P.C.
  • Patent number: 7892883
    Abstract: In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a biasing mechanism to the lid. Heat may be applied to a bond head coupled with a pick and place tool. Heat may be applied to a bond stage coupled to a carrier for holding the package assembly during processing. An adhesive applied to the lid or package substrate may be allowed to at least partially cure. The method may further include, in an oven, reflowing a thermal interface material (TIM) coupled to the lid and the die, curing the TIM, and/or curing the adhesive, without using clips.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: February 22, 2011
    Assignee: Intel Corporation
    Inventors: George Kostiew, Raj Bahadur, James Mellody, George Vakanas, Leonel Arana
  • Patent number: 7894449
    Abstract: A method and apparatus for encoding an identification of a subscriber station and its connections in a data frame for transmission in a wireless communication network comprising at least one base station and at least one subscriber station is disclosed. The method comprises specifying a subscriber station identification in the data frame to identify the one or more subscriber stations for which contents of the data frame are destined and specifying a connection identification in the data frame to identify one or more connections of the one or more identified subscriber stations to which the contents of the data frame belong. The subscriber station identification and the connection identification can be specified in a single stage or in two stages.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: February 22, 2011
    Assignee: Intel Corporation
    Inventor: Shantidev Mohanty
  • Patent number: 7888746
    Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a semiconductor structure having a silicon-on-insulator (SOI) substrate and a dielectric region is disclosed. The dielectric region is adjacent to the active layer of the SOI substrate and the dielectric region includes a portion of a buried oxide (BOX) layer of the SOI substrate. At least a portion of the dielectric region extends from a surface of the active layer of the SOI substrate to a depth of at least about three microns or greater below the surface of the active layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: February 15, 2011
    Assignee: HVVi Semiconductors, Inc.
    Inventor: Michael Albert Tischler
  • Patent number: 7885990
    Abstract: An apparatus and method for providing a source of random numbers are generally described. In one example, an apparatus includes one or more storage elements having a selected voltage and a trip point, the voltage being close enough to the trip point such that random telegraph signal (RTS) noise associated with the elements is a determinant of whether the read voltage is above or below the trip point.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: February 8, 2011
    Assignee: Intel Corporation
    Inventor: Lance W Dover
  • Patent number: 7885220
    Abstract: A method and apparatus of coordinating Time Division Multiple Access operation of wireless communication devices is disclosed. The method comprises an access point announcing a Quiet Period to one or more clients of the access point and transmitting as part of Target Beacons and probe responses an indication to the one or more clients that the access point will be absent from the communication channel for a period of time. The method also comprises the one or more clients establishing a connection with the access point after the Quiet Period when the access point is present on the communication channel on the basis of the indication.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: February 8, 2011
    Assignee: Intel Corporation
    Inventor: Oren Kaidar
  • Patent number: 7885313
    Abstract: A method and apparatus of reducing interference between subsystems implementing wireless communication protocols is disclosed. The method comprises reducing interference in a first subsystem implementing a first wireless communication protocol operating in a first frequency band caused by a second subsystem implementing a second wireless communication protocol operating in a second frequency band, the second wireless communication protocol employing Adaptive Frequency Hopping (AFH), the method comprising calculating one or more frequencies to be avoided by the second subsystem on the basis of one or more frequencies in use by the first subsystem.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: February 8, 2011
    Assignee: Intel Corporation
    Inventors: Giora Rayzman, Miri Ratner
  • Patent number: 7884354
    Abstract: Germanium on insulator (GOI) semiconductor substrates are generally described. In one example, a GOI semiconductor substrate comprises a semiconductor substrate comprising an insulative surface region wherein a concentration of dopant in the insulative surface region is less than a concentration of dopant in the semiconductor substrate outside of the insulative surface region and a thin film of germanium coupled to the insulative surface region of the semiconductor substrate wherein the thin film of germanium and the insulative surface region are simultaneously formed by oxidation anneal of a thin film of silicon germanium (Si1-xGex) deposited to the semiconductor substrate wherein x is a value between 0 and 1 that provides a relative amount of silicon and germanium in the thin film of Si1-xGex.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: February 8, 2011
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Been-Yih Jin, Willy Rachmady, Marko Radosavljevic
  • Patent number: 7880310
    Abstract: A dual-mode integrated circuit comprises wirebondable and solderable electrical connectors.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: February 1, 2011
    Assignee: Intel Corporation
    Inventor: Ranjan J. Mathew
  • Patent number: 7863710
    Abstract: Dislocation removal from a group III-V film grown on a semiconductor substrate is generally described. In one example, an apparatus includes a semiconductor substrate, a buffer film including a group III-V semiconductor material epitaxially coupled to the semiconductor substrate wherein the buffer film includes material melted by laser pulse irradiation and recrystallized to substantially remove dislocations or defects from the buffer film, and a first semiconductor film epitaxially grown on the buffer film wherein a lattice mismatch exists between the semiconductor substrate and the first semiconductor film.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: January 4, 2011
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Peter G. Tolchinsky, Jack T. Kavalieros, Marko Radosavljevic
  • Patent number: 7857139
    Abstract: A front opening unified pod (FOUP) for holding wafers is invertible and compatible with process machines in an inverted orientation. The FOUP can safely transport and store wafers while in a non-upright orientation. The shelves within the FOUP are capable of collapsing and constraining the wafers. Further, a method of holding wafers for processing is provided.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: December 28, 2010
    Assignee: Intel Corporation
    Inventor: Andrew N. Contes
  • Patent number: 7860469
    Abstract: Briefly, in accordance with one or more embodiments, a subscriber station in sleep mode is capable of sending and/or receiving traffic during sleep mode without violating the delay requirements of best effort traffic. Moreover, a subscriber station is capable of remaining in sleep and may optionally only be awaken in the event there is data to be transmitted from the base station to the subscriber station and/or from the subscriber station to the base station. By implementing an always sleep and need based wake up arrangement, the power consumption of the subscriber station can be reduced.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: December 28, 2010
    Assignee: Intel Corporation
    Inventors: Shantidev Mohanty, Muthaiah Venkatachalam
  • Patent number: 7854703
    Abstract: Briefly, in accordance with one or more embodiments, a peripheral neuropathy monitor may be incorporated into a scale form factor or other device for monitoring a trend towards peripheral neuropathy by a monitored user or patient. The peripheral neuropathy monitor may include a heating element, a cooling element, and/or a vibrating element, and may be capable of performing the sensitivity of the user to hot, cold, and/or vibrations, and monitor such trends over time to facilitate detecting the onset of peripheral neuropathy. The peripheral neuropathy monitor may be capable of communicating with a remote device via a wired or wireless network for operating the monitor, and for storing and/or analyzing the test results.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: December 21, 2010
    Assignee: Intel Corporation
    Inventor: David Poisner
  • Patent number: 7853274
    Abstract: Stationary wireless network stations are woken up using Wake-on-WLAN functionality. Wake-on-WLAN is provided by paging stations in a wireless network. Paging may support mobile stations across multiple access points. Paging may also support stationary nodes with reduced overhead. Wake-on-WLAN is also provided to stationary stations in idle mode by signifying a wake-on event in a traffic indication map (TIM). Wake-on events may occur when a station is associated or disassociated with an access point. Upon receiving a wake-on event, a station associates or reassociates with an AP if necessary.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: December 14, 2010
    Assignee: Intel Corporation
    Inventors: Emily H. Qi, James Tsai, Myron Hattig
  • Patent number: 7847350
    Abstract: A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: December 7, 2010
    Assignee: HVVi Semiconductors, Inc.
    Inventor: Robert Bruce Davies
  • Patent number: 7847369
    Abstract: A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: December 7, 2010
    Assignee: HVVi Semiconductors, Inc.
    Inventor: Robert Bruce Davies
  • Patent number: 7843874
    Abstract: A method and apparatus for implementing user defined Link Adaptation solutions in a wireless system.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: Tomasz Madejski, Krzysztof Perycz
  • Patent number: 7843070
    Abstract: Nanotube and metal composite interconnects are generally described. In one example, an apparatus includes an interlayer dielectric (ILD) and one or more interconnect structures coupled to the ILD, the one or more interconnect structures including a composite of metal and one or more nanotubes.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventor: Kevin P. O'Brien
  • Patent number: 7839845
    Abstract: An embodiment of the present invention provides an apparatus, comprising a transmitter capable of compressing header information in an aggregate of Media Access Control Service Data Units (MSDUs) by using one or more flags fields to describe which address fields are present in said aggregate.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: November 23, 2010
    Assignee: Intel Corporation
    Inventor: Adrian P. Stephens
  • Patent number: 7836003
    Abstract: Briefly, in accordance with one or more embodiments, a user experiencing cognitive decline or a similar affliction may be assisted with the performance of daily tasks or routines. An information handling system installed in a central room of the user's living quarters, such as a kitchen, to observe the user and determine if the user is having difficulty completing the task or routine. If it is determined that the user is experiencing difficulty, the information handling system may provide one or more cues to the user to assist the user in remembering what the user has just completed in order to indicate to the user what part of the task remains to be completed. For example, the steps recently taken by the user may be retraced by projecting an image of those footsteps onto the floor to show the user where she has recently been.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: November 16, 2010
    Assignee: Intel Corporation
    Inventors: Terry Dishongh, Simon Roberts, Julie Behan
  • Patent number: 7835187
    Abstract: A method and device using bitline-bitline capacitance between adjacent bitlines to boost seed voltage in a memory device are provided. The method may include a precharge phase, a boost phase, an equalize phase, and a lock in phase. In one embodiment, the method may include boosting the seed voltage twice. The bitlines may be divided into one or more segments.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: November 16, 2010
    Assignee: Intel Corporation
    Inventors: Satoru Tamada, Neal R Mielke, Krishna Parat