Abstract: A cooling system including one or more piezo fans for an electronic assembly is disclosed. The electronic assembly may include heat-generating components coupled with a front side of a printed circuit board (PCB) and one or more piezo fans coupled with a back side of the PCB. One or more piezo fans may be capable of cooling the heat-generating components from the back side. The cooling system may further include a heat sink coupled with the back side of the PCB.
Type:
Grant
Filed:
May 9, 2008
Date of Patent:
June 22, 2010
Assignee:
Intel Corporation
Inventors:
Ioan Sauciuc, Sandeep Ahuja, Ashish Gupta
Abstract: Briefly, in accordance with one or more embodiments, a method of making an inverse-t shaped floating gate in a non-volatile memory cell or the like is disclosed.
Abstract: Briefly, in accordance with one or more embodiments, a hybrid photonics device comprises a silicon portion having one or more features formed therein, a non-silicon portion comprising one or more photonics devices proximate to the one or more features of the silicon portion, and a bonding layer coupling the silicon portion with the non-silicon portion, the non-silicon portion being bonded to the silicon portion via the bonding layer prior to patterning of the one or more photonics devices.
Abstract: Selective program acceleration of a memory device is generally described. A method includes applying a first bias voltage to one or more bit lines coupled with a plurality of cells to be programmed, applying one or more program pulses to the plurality of cells, verifying the plurality of cells at a target threshold voltage to determine whether one or more cells of the plurality of cells have reached or surpassed the target threshold voltage, identifying slower cells of the plurality of cells, and selectively accelerating a program speed of the slower cells to reduce a programming time of a memory device.
Abstract: Techniques associated with providing multiple gate insulator thickness for a semiconductor device are generally described. In one example, an apparatus includes a semiconductor fin having an impurity introduced to at least a first side of the fin, a first oxide having a first thickness coupled with the first side of the fin, and a second oxide having a second thickness coupled with a second side of the fin, the second thickness being different from the first thickness as a result of the impurity introduced to the first side of the fin.
Type:
Grant
Filed:
July 30, 2007
Date of Patent:
May 18, 2010
Assignee:
Intel Corporation
Inventors:
Martin D Giles, David L Kencke, Stephen M Cea
Abstract: Mechanisms for reducing amplitude-modulated noise in a wireless transceiver are generally described. In one example, an apparatus includes a radio-frequency identification (RFID) transceiver, a digital-analog converter (DAC) coupled with the transceiver, a reconstruction filter coupled with the digital-analog converter, and hold logic associated with the reconstruction filter to enable the reconstruction filter to hold its output voltage.
Type:
Grant
Filed:
June 29, 2007
Date of Patent:
April 6, 2010
Assignee:
Intel Corporation
Inventors:
Scott Chiu, Marc Loyer, Thomas J Barnes, Rapp Jan, Jimmy Carlsson
Abstract: A communication device may obtain a channel estimate, and may adjust power thresholds governing an adaptive bit loading scheme. The communication device may include a transceiver arranged to receive data from a remote transmitter on a plurality of subcarriers. The communication device may also include a controller coupled to the transceiver. Finally, a memory unit may be coupled to the controller. The memory unit may contain a set of instructions that when executed cause the controller to cooperate with the transceiver to create a channel estimate, to create modulation criteria based at least in part on the channel estimate, and to command the remote transmitter, on a subcarrier-by-subcarrier basis, to employ a particular modulation technique on a particular subcarrier. Such a command may be based at least in part on a comparison of the channel estimate and the modulation criteria.
Abstract: A system and method of reducing interference in a wireless communication network is disclosed. The method comprises adapting a transmission power of a signal of a wireless communication device when a clear channel assessment threshold equals a predetermined limit and a packet error rate exceeds a predetermined packet error rate threshold. In particular, the method includes increasing the transmission power of the signal when the clear channel assessment threshold equals a lower limit and the packet error rate exceeds an upper packet error rate threshold and decreasing the transmission power of the signal when the clear channel assessment threshold equals an upper limit and the packet error rate falls below a lower packet error rate threshold.
Abstract: Briefly, in accordance with one embodiment of the invention, a wireless device has an array of antennas. A signal is provided to one of the antenna by two variable gain amplifiers, one of which processes a signal that is shifted in phase compared to the signal processed by the other variable gain amplifier.
Abstract: An electronic hybridization assay implements a hybridization reaction, or a sequence analysis, on sequences representative of the sequences of the molecules under examination to provide an output representative of a chemical hybridization reaction. An electronic hybridization machine implements a correlation algorithm where the correlation output provides information regarding the relationship between the molecules under examination. In one aspect, the degree of similarity between the molecules is indicated by the correlation output value. In another aspect, a locus of similarity between the molecules is indicated by a maximum value in the correlation output sequence. In a particular aspect, the sequences are encoded in an optimized format to optimize the operation of the operation of the electronic hybridization machine.
Abstract: Embodiments of multiple input multiple output wireless communication systems, associated methods and data structures are generally described herein.
Type:
Grant
Filed:
December 20, 2005
Date of Patent:
March 2, 2010
Assignee:
Intel Corporation
Inventors:
Xintian E. Lin, Qinghua Li, Keith A. Holt, Raymond Blackham, Minnie Ho
Abstract: In various embodiments, circuits and semiconductor devices and structures and methods to manufacture these structures and devices are disclosed. In one embodiment, a bidirectional polarity, voltage transient protection device is disclosed. The voltage transient protection device may include a bipolar PNP transistor having a turn-on voltage of VBE1, a bipolar NPN transistor having a turn-on voltage of VBE2, and a field effect transistor (FET) having a threshold voltage of VTH, wherein a turn-on voltage VTO of the voltage transient protection device is approximately equal to the sum of VBE1, VBE2, and VTH, that is, VTO?VBE1+VBE2+VTH. Other embodiments are described and claimed.
Abstract: Embodiments of an adaptive in-phase (I) and/or quadrature-phase (Q) imbalance correction for multicarrier wireless communication systems is generally described.
Abstract: A wireless link between a first transmitter and a first receiver in a multiple access communications system is evaluated by receiving, at the first transmitter, information that is intended for a second receiver and that is transmitted in a second transmission mode that is different from the current transmission mode and obtaining an error measure for the information that is received at the first receiver and intended for the second receiver. The obtained error measure is then used to determine if the second transmission mode is an acceptable transmission mode. In an embodiment, if the second transmission mode is determined to be acceptable, then the current transmission mode of the first receiver can be replaced by the second transmission mode. In an embodiment, the current transmission mode is replaced by the second transmission mode only if the second transmission mode is a “higher” transmission mode than the current transmission.
Abstract: Integration of silicon boron nitride in high voltage semiconductors is generally described. In one example, a microelectronic apparatus includes a semiconductor substrate upon which transistors of an integrated circuit are formed, a plurality of transistor gates formed upon the semiconductor substrate, a gate spacer dielectric disposed between the gates, and a contact etch stop dielectric disposed upon the gates and gate spacer dielectric, the contact etch stop dielectric comprising silicon boron nitride (SiBN) to reduce breakdown of the contact etch stop dielectric in high voltage applications.
Abstract: Independent n-tips for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PD devices, and one or more multi-gate pass gate (PG) devices coupled with the semiconductor fin, the one or more PG devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PG devices, wherein the n-tip dopant concentration for the PG device is lower than the n-tip dopant concentration for the PD device.
Type:
Grant
Filed:
November 30, 2007
Date of Patent:
December 8, 2009
Assignee:
Intel Corporation
Inventors:
Ravi Pillarisetty, Suman Datta, Jack T. Kavalieros, Brian S. Doyle
Abstract: A method and circuit for testing phase detectors in a delay locked loop is provided. The method includes storing output from a first phase detector and from a second phase detector when the counter is at the +0, +1, and ?1 counter positions, and comparing the results to determine whether a phase detector is faulty. The circuit implementing this technique uses a second phase detector configured to receive the signals entering a first phase detector. Particularly, the circuit is routed such that a signal entering the D input of the first phase detector is inputted into the clock input of the second phase detector, and a signal entering the clock input of the first phase detector is inputted into the D input of the second phase detector. The circuit is also coupled to a test controller located on-die or at a high volume manufacturing (HVM) tester.
Abstract: A system and method of data transmission in a wireless communication network are disclosed. The method comprises detecting an error in an original transmission and in response thereto, determining that latency sensitive data in the original transmission would be stale when transmitting a copy of the original transmission. The method further comprises transmitting the copy of the original transmission when a retransmission value function at least equals a predetermined threshold and transmitting a new transmission when the retransmission value function is less than the predetermined threshold. The new transmission comprises a copy of the data from the original transmission that is not stale when transmitting the new transmission.
Abstract: A wavelength meter, an associated method, and system are generally described. In one example, an apparatus includes a photodiode to receive an optical signal and to generate a photocurrent upon receiving the optical signal, the photodiode having an absorption edge that is substantially aligned with a band of wavelengths, wherein the absorption edge shifts toward longer wavelengths when a reverse bias is applied to the photodiode, and control electronics coupled with the photodiode to apply at least a first reverse bias and a second reverse bias to the photodiode, wherein a ratio of a first measurement of the photocurrent at the first reverse bias and a second measurement of the photocurrent at the second reverse bias provides information about the wavelength of the optical signal.