Abstract: Briefly, a memory device comprising a beta phase tungsten seed layer is disclosed.

Abstract: Optical die structures and associated package substrates are generally described. In one example, an electronic device includes a package substrate having a package substrate core, a dielectric layer coupled with the package substrate core, and one or more input/output (I/O) optical fibers coupled with the package substrate core or coupled with the build-up dielectric layer, or combinations thereof, the one or more I/O optical fibers to guide I/O optical signals to and from the package substrate wherein the one or more I/O optical fibers allow both input and output optical signals to travel through the one or more I/O optical fibers.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, an electrical bus embedded in a dielectric material below a surface of a semiconductor substrate is disclosed. Other embodiments are described and claimed.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method to manufacture a semiconductor structure includes forming a cavity in a substrate. A portion of the substrate is doped, or a doped material is deposited over a portion of the substrate. At least a portion of the doped substrate or at least a portion of the doped material is converted to a dielectric material to enclose the cavity. The forming of the cavity may occur before or after the doping of the substrate or the depositing of the doped material. Other embodiments are described and claimed.

Abstract: A device capable of remote configuration, provisioning and/or updating comprising a network detector capable of detecting a network regardless of the state of the operating system on the device, wherein the network requires layer two authentication, and an Embedded Trust Agent capable of generating an authentication credential for layer two authentication and communicating the authentication credential via a layer two authentication protocol without a functioning operating system.

Abstract: Briefly, in accordance with one embodiment of the invention, an apparatus comprising Management Frames utilized in wireless communications associated with the apparatus, and the Management Frames being protection-capable or non-protection-capable and wherein the Management Frames indicate whether or not they are protection-capable.

Abstract: An embodiment of this invention combines feed-forward and feedback frequency division circuits in a such a way, to provide greater flexibility in choosing the non-integer division ratios at the output, with little added complexity. Alternate embodiments include additional divider(s) in signal or feedback paths providing additional flexibility and design simplification. An embodiment uses in-phase/quadrature signals to select the desired modes at feedback-path and signal-path mixers. Various alternatives are also described.

Abstract: Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.

Abstract: A method for use with devices in a stacked package is discussed. By preprogramming a unique identifier into a device during manufacture, the device can determine its position in the stack and perform a task based on its position in the stack. In one embodiment, the task is power-up.

Abstract: Techniques associated with higher performance barrier materials for containers to contain one or more environmentally sensitive devices associated with semiconductor manufacture are generally described. In one example, an apparatus includes an enclosure to contain one or more environmentally sensitive devices associated with semiconductor manufacture, the enclosure comprising a liquid crystal polymer (LCP) to provide a barrier against at least water and oxygen and to reduce purging requirements, and a door coupled with the enclosure.

Abstract: Using controlled bias voltage for data retention enhancement in a ferroelectric media is generally described. In one example, an apparatus includes a ferroelectric film including one or more domains, the ferroelectric film having a first surface and a second surface, the first surface being opposite the second surface, an electrode coupled with the first surface, and an electrically conductive thin film coupled with the second surface wherein the electrically conductive thin film is sufficiently conductive that a controlled bias field applied between the electrically conductive thin film and the electrode is sufficient to grow, shrink, or actively maintain the size of the one or more domains disposed between the electrically conductive thin film and the electrode.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least a portion of the dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material. Other embodiments are described and claimed.

Abstract: Briefly, in accordance with one or more embodiments, a digital transmitter may comprise two or more phase modulators in a cascaded arrangement. The phase modulators may modulate a local oscillator signal using control signals derived from the quadrature baseband data to be transmitted. A closed loop power control feedback arrangement may be used to compare the output power of the transmitter with a desired output signal, and make corrections to the output signal by modifying at least one of the control signals provided to the cascaded phase modulators.

Abstract: A processor starting a duty cycle timer with a specified duty cycle period and a specified power state, and if the duty cycle timer expires, placing the processor in the specified power state in response to the expiry of the timer, if the timer has not expired and if an interrupt other than a timer tick interrupt is received, canceling the duty cycle timer in response to the interrupt other than a timer tick interrupt.

Abstract: A memory device including current-limiting circuitry coupled to a first inverter inside a data register is provided. The current-limiting circuitry controls a voltage supplied to the first inverter and a reference voltage may be adjusted so that the voltage supplied to the first inverter is prevented from dropping below a voltage supplied to a second inverter inside the data register. The memory device may include a switch to allow coupling to the current-limiting circuitry for programming of the memory device.

Abstract: Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.

Abstract: Techniques associated with surface treatments for photomasks, semiconductor wafers, and/or optics are generally described. In one example, a method includes preparing a surface of a photomask or semiconductor wafer for cleaning, and removing ionic contamination from a surface of a photomask or semiconductor wafer using radical or atomic hydrogen, or suitable combinations thereof, to reduce the ionic contamination, wherein removing ionic contamination reduces the number of defects and increases semiconductor product yields accordingly.

Abstract: Methods for consistent updates to APC models with partitioning along multiple components are generally described. In one example, a method includes acquiring measurement data from one or more semiconductor wafers of a processed first lot, the data having a plurality of contexts, applying a model having parameters with partitioning along the contexts to the measurement data; and applying a constraint on a subset of the model parameters such that the subset remains centered around zero to provide consistent updates for automated process control of lots processed after the first lot.

Abstract: A method and communication system for selecting a mode for encoding data for transmission in a wireless communication channel between a transmit unit and a receive unit. The data is initially transmitted in an initial mode and the selection of the subsequent mode is based on a selection of first-order and second-order statistical parameters of short-term and long-term quality parameters. Suitable short-term quality parameters include signal-to-interference and noise ratio (SINR), signal-to-noise ratio (SNR), power level and suitable long-term quality parameters include error rates such as bit error rate (BER) and packet error rate (PER). The method of the invention can be employed in Multiple Input Multiple Output (MIMO), Multiple Input Single Output (MISO), Single Input Single Output (SISO) and Single Input Multiple Output (SIMO) communication systems to make subsequent mode selection faster and more efficient.

Abstract: A current sensing scheme for non-volatile memory is disclosed comprising an apparatus for determining one or more memory cell states in a non-volatile memory device. The apparatus having a first memory cell coupled to a first bitline and a first sensing element coupled to the first bitline, the first sensing element operable to sense a voltage corresponding to a state of the memory cell wherein the sensed voltage is independent of a bitline voltage discharge over time of the first memory cell.