Abstract: A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication.

Abstract: A method and apparatus of coordinating operation of subsystems implementing different wireless communication protocols is disclosed. The method comprises coordinating operation of a first subsystem implementing a first wireless communication protocol and at least other subsystem implementing at least one other wireless communication protocol by arbitrating between conflicting real time requests for access from the first subsystem and the at least one other subsystem based on a respective type and priority of the requests.

Abstract: Feedback bandwidth may be reduced in a closed loop MIMO system by Householder transformations, vector quantization using codebooks, and down-sampling in the frequency domain. A column of a beamforming matrix is quantized using a codebook, a Householder reflection is performed on the beamforming matrix to reduce the dimensionality of the beamforming matrix, and the quantizing and performing of Householder reflection on the previously dimensionality reduced beamforming matrix is recursively repeated to obtain a further reduction of dimensionality of the beamforming matrix. These actions are performed for a subset of orthogonal frequency divisional multiplexing (OFDM) carriers, and quantized column vectors for the subset of OFDM carriers are transmitted.

Abstract: A lost or stolen computing device is recovered. A trusted server is requested to locate the computing device. The trusted server requests coarse location information from the computing device, and the computing device reports its coarse location. The trusted server then requests that the computing device transmit wireless local area networks signal so that it may be recovered.

Abstract: Classification of spatial patterns on wafer maps is generally described. In one example, a method includes applying K-means type clustering to wafer maps comprising one or more spatial patterns to group one or more clusters comprising wafer maps having similar spatial patterns and producing a dendrogram using a clustering process to display the one or more clusters.

Abstract: Briefly, in accordance with one or more embodiments, parallel DFE processing may be utilized for single carrier systems that employ cyclic prefixes. The achieved parallelism allows working at contemporary clock rates that are significantly lower than the required sampling rate at high bandwidth systems such as 60 GHz transmissions.

Abstract: A method and communication system for selecting a mode for encoding data for transmission in a wireless communication channel between a transmit unit and a receive unit. The data is initially transmitted in an initial mode and the selection of the subsequent mode is based on a selection of first-order and second-order statistical parameters of short-term and long-term quality parameters. Suitable short-term quality parameters include signal-to-interference and noise ratio (SINR), signal-to-noise ratio (SNR), power level and suitable long-term quality parameters include error rates such as bit error rate (BER) and packet error rate (PER). The method of the invention can be employed in Multiple Input. Multiple Output (MIMO), Multiple Input Single Output (MISO), Single Input Single Output (SISO) and Single Input Multiple Output (SIMO) communication systems to make subsequent mode selection faster and more efficient.

Abstract: A memory device and a method to prevent or reduce program disturb by isolating P-wells of strings in a non-volatile memory array. During a program operation, the isolated P-wells may be coupled to corresponding bitlines, which may be selected or inhibited, and may be at different voltages. During erase, read, and verify operations, the isolated P-wells may be coupled to source.

Abstract: The present invention includes a method of optimizing a transmission mode of wirelessly transmitted data. The method includes selecting a first transmission mode based on a predetermined channel database and a first channel characterization. The first channel characterization can be based upon signals transmitted in an initial mode. An error factor is generated based on a difference between an estimated performance characteristic, and an expected performance characteristic. A subsequent transmission mode is selected based upon the predetermined channel database, the error factor and a subsequent channel characterization. The predetermined channel database can include a predetermined look-up-table that provides transmission mode selections based upon the channel characterizations. The look-up-table generally includes a plurality of quality parameter thresholds that determine the selection of a transmission mode.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.

Abstract: Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated circuit (IC) pattern in the first photoresist, the first IC pattern comprising one or more trench structures, protecting the first IC pattern in the first photoresist from actions that form a second IC pattern in a second photoresist, depositing the second photoresist to the first IC pattern, and forming the second IC pattern in the second photoresist, the second IC pattern comprising one or more structures that are sufficiently close to the one or more trench structures of the first IC pattern to cause scumming of the second photoresist in the one or more trench structures of the first IC pattern.

Abstract: A memory device including current-limiting circuitry coupled to a first inverter inside a data register is provided. The current-limiting circuitry controls a voltage supplied to the first inverter and a reference voltage may be adjusted so that the voltage supplied to the first inverter is prevented from dropping below a voltage supplied to a second inverter inside the data register. The memory device may include a switch to allow coupling to the current-limiting circuitry for programming of the memory device.

Abstract: An embodiment of the present invention provides a method, comprising reducing overhead in OFDMA based Wireless Networks by determining the highest CIDs to be transmitted in a particular DL/UL MAP and determining the number of leading zero bits of the highest CID and removing the leading zero bits from each CID prior to transmission. Further, an embodiment of the present invention provides removing the CID field in the header of the message identified by a particular CID.

Abstract: A method and circuit for testing phase interpolators is provided. The method performs a sweep over a phase interpolator delay range and detects if the phase interpolators experience an unacceptably large non-linearity which leads to inaccurate clock timing. The testing circuit implementing this technique uses a phase detector to detect a fault, and in one embodiment, an additional phase interpolator is added as well.

Abstract: A conditional payload header suppression is disclosed to improve compression, by providing the flexibility to dynamically introduce fields/header bytes, which change temporarily or infrequently in packets. The embodiment also uses a dynamic mask as part of the payload header suppression packet to indicate which of the conditionally suppressed header bytes are present in the packet sent over the air or the communication medium. An embodiment of this invention increases the header compression for packets such as IP/UDP/RTP (VOIP) and TCP ACK in communication networks, such as WiMax.

Abstract: A die storage method and apparatus comprising a cover tape and a strip coupled to the cover tape wherein the strip comprises a material that is: flexible or compressible, or combinations thereof.

Abstract: Methods and apparatus for transmitting packets in wireless communication networks are disclosed. The methods include a relay mobile station measuring channel quality between the relay mobile station and a destination mobile station in response to a request for relay mobile stations from a base station The relay mobile station reports a channel quality indicator to the base station if the channel quality for a link between the base station and the destination mobile station via the relay mobile station is greater than a predetermined channel quality. The base station determines the relay mobile station that provides an optimal route for transmitting the packets from the base station to the destination mobile station.

Abstract: Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.

Abstract: A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

Abstract: A circuit for testing phase detectors in a delay locked loop is provided. The circuit uses a second phase detector arranged to receive the signals entering a first phase detector. Particularly, the circuit is routed such that a signal entering the D input of the first phase detector is inputted into the clock input of the second phase detector, and a signal entering the clock input of the first phase detector is inputted into the D input of the second phase detector. The circuit is also coupled to a test controller located on-die or at a high volume manufacturing (HVM) tester.