Abstract: A semiconductor device (10) is formed in a pedestal structure (16) overlying an epitaxial layer (12) and a semiconductor substrate (11). The semiconductor device (10) includes a doped region (13) that forms a PN junction with the epitaxial layer (12). The semiconductor device (10) also includes a dielectric layer (22) that has an opening (23) that exposes a portion of the doped region (13) and an opening (24) that exposes a portion of the epitaxial layer (12). The openings (23, 24) are filled with a conductive material (36, 37) to provide contacts (100, 101). Due to the presence of the PN junction, the contacts (100, 101) are capacitively coupled to each other.

Abstract: To generate a stereoscopic image of an object (41), two light beams (151, 161) unparallel to each other are used to back light a portion (43) of the object (41). The two light beams (151, 161) are deflected to form two deflected light beams (153, 163) substantially parallel to each other. The deflected light beams (153, 163) form a stereoscopic image of the portion (43) of the object (41). A camera (46) records the stereoscopic image of the object (41). The signal from the camera (46) is processed by a vision computer (48) to reconstruct the stereoscopic image and determine whether the object (41) meets design specifications.

Abstract: A method for forming a semiconductor sensor device comprises providing a substrate (4) and forming a sacrificial layer (18) over the substrate. The sacrificial layer (18) is then patterned and etched to leave a portion (19) on the substrate (4). A first isolation layer (6) is formed over the substrate (4) and portion (19) of the sacrificial layer and a conductive layer (12), which provides a heater for the sensor device, is formed over the first isolation layer (6). The portion (19) of the sacrificial layer is then selectively etched to form a cavity (10) between the first isolation layer (6) and the substrate (4), the cavity (10) providing thermal isolation between the heater and the substrate.

Abstract: A method for packaging a semiconductor device (22) formed on a die (12) having opposing major surfaces includes pre-soldering the die (12) at wafer level using an electroplating process, wherein the die (12) has solder bumps disposed on each opposing major surface. The pre-soldered wafer (10) is then diced into pre-soldered dies. The die (12) is placed in a glass sleeve (45) and aligned with two bumpless lead assemblies (46, 48). The bumpless lead assemblies (46, 48) are solder bonded to the die (12) via a reflow process. The reflow process also partially melts the glass sleeve (45), thereby forming a hermetically sealed glass capsule (55) surrounding the semiconductor device (22).

Abstract: A smartcard (10) is formed in part by a laminate layer (77). The laminate layer (77) is made up of a plurality of dielectric layers (11,30), insulating layers (45, 50), resistive layers (55), and electrically active structures. The electrically active structures include a capacitive structure (23) which is formed from one of the dielectric layers (11) and an antennae (32) which is made from a conductive layer that is formed into a spiral pattern on the another dielectric layer (30). These layers (11,30, 45, 50, 55) are formed separately and then pressed together to form the laminate layer (77).

Abstract: A field effect transistor (10) for chemical sensing by measuring a change in a surface potential of a gate electrode (48) due to exposure to a fluid has a semiconductor substrate (12) with a trench (18,20). The trench has a first sidewall (30) and a second sidewall (32) disposed opposite the first sidewall to provide a fluid gap (50) for the fluid to be sensed. The gate electrode is disposed overlying the first sidewall of the trench, and a source region (54) and a drain region (56) are disposed in the second sidewall of the trench. A channel region (52) is disposed between the source and drain regions, and the gate electrode is disposed opposite the first channel region across the fluid gap. A heater (26) for regulating the temperature of the gate electrode is disposed in the first sidewall of the trench.

Abstract: An electrical insulation for a heatsink (14) of a semiconductor device (10) is provided by an insulating layer (16) formed on a desired portion or portions of the semiconductor device (10) to protect a semiconductor die (17) from arcing currents due to high voltage potentials. The insulating layer (16) is formed from a non-conductive powder coating which is applied to the semiconductor devices (10) by attracting the powder to the semiconductor device (10) in one of four ways. Either a fluidized powder bed process, an electrostatic fluidized bed process, an electrostatic spraying process, or the powder is applied during the mold process on the desired surface of the semiconductor device (10). Once the powder coating is applied to the heatsink (14), the semiconductor package is cured to form the insulating layer (16). The insulating layer (16) can also be formed over other portions the semiconductor device (10) such as a body (13), leads (12), or a leadframe (11).

Abstract: The programming time of a non-volatile memory cell (13) is reduced by forming the non-volatile memory cell (13) in a well region (12). The presence of the well region (12) increases the number of electrons that are present in a channel region (14) of the non-volatile memory cell (13). The number of electrons in the channel region (14) is also increased by placing a voltage potential on the well region (12) relative to a source region (15). The voltage differential will inject electrons into the well region (12), which increases the number of electrons in the channel region (14).

Abstract: A sensor (10,30) is formed that does not require a bonding process in an oxygen rich or vacuum ambient. In a first embodiment, a port (14), a channel (15) and an opening (18) are used to provide an oxidizing ambient to a cavity (13). During an oxidation process, the cavity (13) is sealed and any remaining oxidizing ambient is consumed to form a sealed cavity that is under a vacuum pressure. In an alternate embodiment, a cavity (32) is formed in a first substrate (31). The cavity (32) is covered by a second substrate (36) and an opening (33,34) is formed in the second substrate (36) above the cavity (32). These openings (33,34) allow an oxidizing ambient to enter the cavity (32).

Abstract: Trench structures (12,32,35,46) are formed in single crystal silicon substrates (10,30) that have either a (110) or (112) orientation. A selective wet etch solution is used that removes only the exposed portions of the single crystal silicon substrates (10,30) that are in the (110) or (112) crystal planes. The trench structures (12,32,35,46) are defined by the {111} crystal planes in the single crystal silicon substrate (10,30) that are exposed during the selective wet etch process. Trench structures (32,35) can be formed on both sides of a single crystal silicon substrate (30) to form an opening (34). Opening (34) can be used as an alignment mark to align front side processing to backside and vice versa. Trench structures can also be use to form a microstructure (41,61) for a sensor (40,60).

Abstract: An n-channel device (10) and a p-channel device (11) are formed from a single epitaxial silicon layer (60,61). During the deposition of the single epitaxial silicon layer (60,61), dopants are added to the epitaxial reaction chamber and subsequently changed to define a drain region (24,33), a channel region (27,34), and a source region (30,35). The dopant concentration is modified during the formation of the channel region (27,34) to create a doping profile (50). The doping profile (50) has a first profile (51) that is constant and a second profile (52) that changes.

Abstract: A first pattern of bumps and a second pattern of bumps are formed on a substrate (10) with bumps (14,15). During a transfer process, only the bumps (14) of the first pattern of bumps are transferred to pad extensions (20) of a device (17). The bumps (15) of the second pattern of bumps are not affected by this process and can be later transferred to a second device.

Abstract: Real time distance and pressure data of a plunger (35) relative to a mold compound is provided by a compensation assembly (29) in a mold press (10). The compensation assembly has a sliding block assembly (30) which moves substantially in the same direction as the plungers (35). The sliding block assembly (30) has pressure control cylinders (33) which limit the pressure plungers (35) can apply. If the pressure on the plungers (35) should exceed this limit, the plungers (35) retract towards the sliding block assembly (30). A sensor (37) is coupled between the sliding block assembly (30) and the plungers (35) to measure the distance the plungers have moved towards the sliding block assembly (30). In one application, the sensor (37) is formed from a linear voltage displacement transducer (LVDT) so the mold press (10) can have real time pressure and distance data.

Abstract: A material (21) is transferred to an electronic component (32) using a transfer apparatus (10). The transfer apparatus (10) has pins (13) that pass through openings (19) in a cavity plate (16). The pins (13) and the openings (19) in the cavity plate (16) form cavities (20) that are filled with the material (21). The pins (13) are then extended from the cavity plate (16) to transfer the material (21) from the cavities (20) to the electronic component (32).

Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60, 97) that can be used to transport electrical signals across the device (10).

Abstract: A method for flip-chip bonding of two electronic components (27,28) does not use a flux material. A substrate (13) of one electronic component (28) is roughened during processing to provide an improved adhesive surface for a solder ball (12). The roughened pattern is replicated by additional conductive layers formed over the substrate or in an alternate embodiment may be formed on one of the intermediary or top conductive layers. Tacking pressure is applied to the two components so the solder ball (12) will be affixed to the roughened surface and provide a temporary bond. This bond ensures the surfaces of the two electrical components remain in contact with each other during reflow of the solder ball (12) to form a permanent bond.

Abstract: Portions of a semiconductor device (10,30) are formed from a dielectric layer (16,38,46) which is deposited using a plasma enhanced chemical vapor deposition (PECVD) process which adds trimethylphosphite as a dopant source during the deposition. A first embodiment forms sidewall spacers (17) adjacent to a gate structure (14) and forms doped regions (19) under the sidewall spacers (17) by annealing the dielectric layer (16) and driving phosphorus into a substrate (11). A second embodiment uses the trimethylphosphite doped film as an interlevel dielectric layer (38) which can be planarized to provide a flat surface for the formation of metal interconnect lines. A third embodiment of the present invention uses the trimethylphosphite doped film as a passivation layer (46) which is deposited in a single step process and has a phosphorus concentration to getter mobile ions.

Abstract: A sensor (10) is capable of detecting linear acceleration in the three Cartesian directions and the angular acceleration about three Cartesian axes. The sensor (10) has a conductive layer (32) that is free to move or rotate in any direction. A first, second, and third set of conductors are used to sense and quantify the acceleration of the conductive layer (32). The sensor (10) can also be operated as a closed loop system with the addition of a fourth set of conductors.

Abstract: A package assembly (31) has a leadframe (10) including a locating flange (30), an optical transmitter (22) such as a laser diode mounted to the leadframe, and a package (32) enclosing both the optical transmitter and a portion of the leadframe so that the locating flange of the leadframe is disposed outside of the package. The locating flange is used as a reference datum to align the optical transmitter's relative height and lateral position during manufacture. Also, the locating flange is used as a reference datum in mating the package assembly to other, standard optical components when mounting to other components in an optical end product.

Abstract: An electronic component assembly (10) is formed by mounting an electronic component (31) to a substrate (11). An encapsulating material (33) is used to protect the electronic component (31) from environmental hazards. The encapsulating material (33) is formed by dispensing an encapsulating fluid over the electronic component (31). A trench (36) is formed in a masking layer (21) on a substrate (11) to stop the flow of the encapsulating fluid. The trench (36) provides an edge (35) which acts as a discontinuity in the surface (23) of the masking layer (21). This discontinuity is sufficient to control the flow of the encapsulating fluid until the encapsulating fluid is cured to form the encapsulating material (33).