Abstract: In a trench-gated MOSFET including an epitaxial layer over a substrate of like conductivity and trenches containing thick bottom oxide, sidewall gate oxide, and conductive gates, body regions of the complementary conductivity are shallower than the gates, and clamp regions are deeper and more heavily doped than the body regions but shallower than the trenches. Zener junctions clamp a drain-source voltage lower than the FPI breakdown of body junctions near the trenches, but the zener junctions, being shallower than the trenches, avoid undue degradation of the maximum drain-source voltage. The epitaxial layer may have a dopant concentration that increases step-wise or continuously with depth. Chained implants of the body and clamp regions permits accurate control of dopant concentrations and of junction depth and position. Alternative fabrication processes permit implantation of the body and clamp regions before gate bus formation or through the gate bus after gate bus formation.

Abstract: A time scaling process for a multi-channel (e.g., stereo) audio signal uses a common time offsets for all channels and thereby avoids fluctuation in the apparent location of a sound source. In the time scaling process, common time offsets correspond to respective time intervals of the audio signal. Data for each audio channel is partitioned into frames corresponding to the time intervals, and all frames corresponding to the same interval use the same common time offset in the time scaling process. The common time offset for an interval can be derived from channel data collectively or from separate time offsets independently calculated for the separate channels. Preprocessing can calculate the common time offsets for inclusion in an augmented audio data structure that a low-processing-power presentation system uses for real-time time scaling operations.

Abstract: Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

Abstract: Smart selection and paste operations for image processing use a wide edge area for selection and masking of an object from a source image. The wide edge area, which can be designated with a brush tool, allows a user to select all of a desired object without requiring pixel-by-pixel identification of the objects edge. A masking unit operates on the edge area and designates each portion or pixel of the edge area as being foreground, background, or a combination of foreground and background. The mask unit constructs a mask and a pixel map for the selected object. The mask is an array of blending parameters, and the pixel map contains natural foreground colors generated by removing background contributions form portions designated as combinations of foreground and background. A paste operation uses the blending parameters from the mask to add background contributions from a target images to the portions of the object designated as combinations of foreground and background.

Abstract: A “chained implant” technique forms a body region in a trench gated transistor. In one embodiment, a succession of “chained” implants can be performed at the same dose but different energies. In other embodiments different doses and energies can be used, and particularly, more than one dose can be used in a single device. This process produces a uniform body doping concentration and a steeper concentration gradient (at the body-drain junction), with a higher total body charge for a given threshold voltage, thereby reducing the vulnerability of the device to punchthrough breakdown. Additionally, the source-body junction does not, to a first order, affect the threshold voltage of the device, as it does in DMOS devices formed with conventional diffused body processes.

Abstract: A register file structure efficiently handles matrix and image processing. The register file contains an array of data elements and has modes for accessing of multiple data values that are aligned horizontally or vertically in a data array and for accessing data having different widths for each data value. The different modes allow manipulation of a transposed array without requiring a transpose operation and permit fast horizontal or vertical filtering with parallel access and multiplications of horizontally or vertically aligned data elements.

Abstract: Media encoding, transmission, and playback processes and structures employ a multi-channel architecture with different audio channels corresponding to different playback rates for a presentation to be transmitted over a network. Audio frames in the various audio channels all correspond to the same amount of time in the original presentation and have frame indexes that identify in the different audio channels the frames corresponding to the same time interval in the presentation. A user can make a real-time change in playback rate causing selection of a channel corresponding to the new playback rate and a frame required for prompt and smooth transition in the playback rate of the presentation. The architecture can additionally provide channels for graphics data such as image data that are displayed according to the index of the audio, and different audio channels with the same playback rate but different compression schemes for use according to available bandwidth on the network.

Abstract: Systems and methods for generating three-dimensional models of an object use images having unmeasured camera parameters. Camera calibration determines the perspective of the camera from the content of the images. A background having a pattern with a known marks in each image can facilitate determination of the camera parameters. One background pattern includes separated marks having rectangular sections where corners of the rectangular sections provide calibrations points for the camera parameters. The camera parameters can also be determined by matching features of the object in different images and determining differences in perspective from differences in the appearance of the matched features in different images. A combination of projective and metric reconstructions provides robust reconstruction.

Abstract: One embodiment of the present invention is a structure useful for testing circuits that includes: (a) a flexible substrate having contactors on a first side and pads on a second side; (b) a rigid substrate having vias aligned with the pads on the second side of the flexible substrate; (c) an adhesive layer comprised of a compliant adhesive material having vias aligned with the pads on the second side of the flexible substrate; the adhesive layer being affixed to the flexible substrate and the rigid substrate; (d) a card; (e) electrical connectors that are retained in the vias of the rigid substrate and the adhesive layer, which electrical connectors have first and second retractable ends, wherein the first retractable ends contact pads on the substrate, and the second retractable ends contact pads on the card; and (f) a clamp that is adapted to fit over the substrate and the adhesive layer, the clamp having an opening to provide access to the contactors, wherein the clamp is connected to the card.

Abstract: A probing system or process for electrical testing of a device fabricated on a wafer also conditions terminals such as solder balls on the device to improve uniformity of the heights of the terminals and improve the reliability of connections to an interconnect substrate in a flip-chip package or to a printed circuit board in a chip-on-board application. The system can employ a probe card that is a printed circuit board and/or is substantially identical to interconnect substrates used in flip-chip packaging. The probe card can be replaceable on a test head to allow for quick changes the reduce ATE downtime and to accommodate device changes such as a die shrink. Probe tips on the probe card can be the contact pads or bumps that are the normal electrical contact structures of the interconnect substrates.

Abstract: The planarity of external terminals or a ball grid array on a device package can be improved through use of test probes that flatten the electrical terminals while forming the electrical contacts for package testing. After testing, the package has external terminals with improved planarity that improves the electrical connections formed during assembly of a system containing the package.

Abstract: Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

Abstract: A photo-ionization detector having an adjustable drive power for a UV lamp implements a calibration operation that determines measurement signals for a series of drive power levels and based on the resulting measurement signals selects one or more drive power levels for normal operation of the PID. The calibration operation permits use of UV lamps having a wider range of performance levels and thereby improves manufacturing yields and extends the useful life of the PID. During normal operation, the PID further fine-tunes the drive power level to compensate for expected or measured degradation in lamp performance. Accordingly, between calibrations, the PID maintains a more uniform UV intensity for more accurate measurements. To expand the measurement range of the PID, the calibration process can select two or more power levels for use when measuring different gas concentrations.

Abstract: A driving shaft for a ratchet spanner includes a shaft body and a sleeve-retaining member. The shaft body includes a polygonal driving end that is adapted to be received fittingly within a wrench sleeve and that has an end surface with a polygonal screwdriver-engaging groove adapted for receiving a head of a screwdriver fittingly, and an annular outer surface that is formed with a hole communicated with the screwdriver-engaging groove in the end surface. A sleeve-retaining member is disposed within the screwdriver-engaging groove in the shaft body, and has an integral projection that extends through the hole in the shaft body and that is adapted to be biased to press against the wrench sleeve so as to retain the wrench sleeve on the driving end of the shaft body.

Abstract: A paintball carrying and loading device or pod includes a cushion to avoid rattling, impact, and breaking of paintballs when the device is carried on a field of play. The device generally includes a tube, a lid, and the cushion. The cushion can be removable or attached to the lid or to a closed end of the tube. A second cushion can provide cushioning at the other end of the tube.

Abstract: One embodiment of the present invention is a structure useful for testing circuits that includes: (a) a substrate having contactors on a first side and pads on a second side; (b) a card having pads on a first side; and (c) interconnectors that electrically connect the pads on the second side of the substrate with the pads on the card; wherein at least one of the interconnectors includes at least a portion that does not melt at temperatures in a range from about 183° C. to about 230° C., and the distance between the substrate and the card is determined by a dimension of the at least a portion.

Abstract: A dam or barrier around the periphery of a die in a flip-chip package changes the shape of the underfill to reduce stress resulting from edge effects. The dam can include a treated region of a substrate having an affinity to an underfill material. The treated region causes liquid underfill material to bead, thereby controlling the wetting angle of the underfill material and shaping the underfill to eliminate sources of stress such as underfill fillet regions that are subject to significant shrinkage. The dammed underfill additionally avoids or reduces the extent of areas having thermal coefficients of expansion that differ from the optimal level because of low filler particle concentration.

Abstract: A trench-gated MOSFET formed using a super self aligned (SSA) process employs an insulating layer such as a glass layer and a contact mask to define contact openings for electrical connections to source regions of the MOSFET. Use a contact mask and an intervening glass in otherwise self-aligned process reduces the coupling capacitance between source metal and the top of the embedded trench gate. A metal layer deposited to make electrical contact to source regions can be planarized, for example, ground flat using chemical-mechanical polishing to provide a flat surface to avoid formation of conductive traces that extend over the steps that the glass layer forms.

Abstract: One embodiment of the present invention is a structure useful for testing circuits that includes: (a) a flexible substrate having contactors on a first side and pads on a second side; (b) a rigid substrate having vias aligned with the pads on the second side of the flexible substrate; (c) an adhesive layer comprised of a compliant adhesive material having vias aligned with the pads on the second side of the flexible substrate; the adhesive layer being affixed to the flexible substrate and the rigid substrate; (d) a card; (e) electrical connectors that are retained in the vias of the rigid substrate and the adhesive layer, which electrical connectors have first and second retractable ends, wherein the first retractable ends contact pads on the substrate, and the second retractable ends contact pads on the card; and (f) a clamp that is adapted to fit over the substrate and the adhesive layer, the clamp having an opening to provide access to the contactors, wherein the clamp is connected to the card.

Abstract: A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. An erase operation can use a negative voltage on the control and a positive voltage on an underlying well or source/drain region to cause tunneling that discharges one or both floating gates. Applying a limited current to a source/drain region during an erase operation can cause the source/drain region and a floating gate to rise together and avoid band-to-band tunneling and resulting hole injection into the floating gate.