Abstract: A row decoder driver in a semiconductor memory device includes a first MOS transistor. The first MOS transistor includes a first source area having a width equal to an integral multiple of a memory cell pitch, and a first drain area having a width equal to the integral multiple of the memory cell pitch. The first drain area is adjacent to the first source area with a first gate area formed between the first source area and the first drain area. The gate area and an underlying channel region extend in a direction perpendicular to the direction of a wordline. First source contacts are in the first source area, and first drain contacts are in the first drain area, facing the first source contacts across the first gate area. This placement of source and drain contacts increases the efficiency of the MOS driver. Therefore, important properties such as tRCD and tRP in a synchronous DRAM are improved, and a standby current in the row decoder driver is reduced.

Abstract: A semiconductor memory device precharges IO lines of the device rapidly at a write interrupt in normal and full page modes. The device includes a write interrupt detector, a precharge signal generator, and a precharge circuit. The write interrupt detector detects whether signals indicating a write interrupt in the normal mode are from the outside, and then generates a write interrupt detection signal. The precharge signal generator generates first and second precharge signals in response to the write interrupt detection signal, and the precharge circuit precharges IO lines at both sides of a memory cell array of the device before a read or write operation in the normal mode in response to the first and second precharge signals. Since the address access time of the semiconductor memory device is short, a high-speed semiconductor memory device can be implemented using the present invention.

Abstract: A clamp holds a semiconductor wafer during an Al reflow process. The clamp is made of a ceramic material, and thereby clamp surface roughening which damages semiconductor wafers and other damaging of the wafer caused by the deformation of the clamp are avoided. A sloped surface of the clamp pad can also reduce the damage on the wafer by reducing the contact area between the clamp pad and the wafer. In addition, the clamp has several features that can reduce heat dissipation from the wafer to outside during the Al reflow. Slots formed on the pad reduce the amount of heat conduction through the clamp, and the polished inner surface of the clamp cap reflects the heat radiated from the wafer back to the wafer.

Abstract: Die-bonding equipment and a method for detecting adhesive dotting on a substrate are disclosed. A dotted adhesive pattern illustrating an actually dotted state of the adhesive on a substrate is overlap-photographed with a standard pattern illustrating proper dotting pattern. The overlap-photographed pattern is compared with a standard overlap pattern. According to the compared result, whether the adhesive is properly dotted on the substrate is decided. When the adhesive is not properly dotted, an alarm signal is generated.

Abstract: In accordance with the present invention, a chip scale package (CSP) is manufactured at wafer-level. The CSP includes a chip, a conductor layer for redistribution of the chip pads of the chip, one or two insulation layers and multiple bumps, which are interconnected to respective chip pads by the conductor layer and are the terminals of the CSP. In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer is provided. The reinforcing layer absorbs stress applied to the bumps when the CSP are mounted on a circuit board and used for an extended period, and extends the life of the bumps, and thus, the life of the CSP. The edge protection layer and the chip protection layer prevent external force from damaging the CSP. After forming all elements constituting the CSP on the semiconductor wafer, the semiconductor wafer is sawed to produce individual CSPs.

Abstract: Disclosed is a high dielectric capacitor composition consisting of Pb(Fe1/2Nb1/2)O3, Pb(Fe1/2Ta1/2)O3, Pb(Ni1/3Nb2/3)O3 and Pb(Zn1/3Nb2/3)O3 in association with manganese nitrate (Mn(NO3)2.4H2O). It has a dielectric constant of 10,000 or higher with a relatively low loss factor of 2.6% or less, showing the temperature properties of Y5V.

Abstract: A postfiltering process for improving the appearance of a video image includes motion compensated temporal filtering and spatial adaptive filtering. For each target pixel being filtered, the temporal filtering uses multiple motion vectors and one or more pixel values for a prior frame to determine one of more reference values for the target filter. In one embodiment, a weighted average of multiple motion vectors for blocks near or containing the target pixel value provides a filter vector that points to a pixel value in the prior frame. This pixel value is a reference value for the target pixel value and is combined with the target pixel value in a filter operation. Alternatively, multiple motion vectors for blocks near or containing the target pixel value point to pixel values in the prior frame that are averaged to determine a reference value for the target pixel value. In each alternative, the weighting for the average is selected according to the position of the target pixel value.

Abstract: A self aligned contact pad in a semiconductor device and a method for forming the self aligned contact pad are disclosed. A bit line contact pad and a storage node contact pad are simultaneously formed by using a photoresist layer pattern having a T-shaped opening including at least two contact regions. An etch stopping layer is formed over a semiconductor substrate and over a transistor. An interlayer dielectric layer is then formed over the etch stopping layer. Next, the interlayer dielectric layer is planarized to have a planar top surface. A mask pattern having a T-shaped opening is then formed over the interlayer dielectric layer, exposing the active region and a portion of the inactive region. The interlayer dielectric layer and etch stopping layer are sequentially etched to reveal a top surface of the semiconductor substrate using the mask pattern, thereby forming a self aligned contact opening exposing a top surface of the semiconductor substrate. The mask pattern is then removed.

Abstract: To reduce latency on a shared bus during bus arbitration, a novel shared bus system uses device select lines between a bus arbiter and the bus devices to select the bus slave concurrently with the granting of the shared bus to the bus master. Specifically, a bus device requests the use of the shared bus by driving an active state on a bus request terminal and driving a destination ID value corresponding to the desired bus slave to the bus arbiter. The bus arbiter then drives an active state on a bus grant output terminal coupled to the bus grant input terminal of the requesting device. Concurrently, the bus arbiter drives an active state on the device select output terminal coupled to the device select input terminal of the desired bus slave. In addition posted read request tagging can be simplified using a transaction ID bus to supplement the shared bus.

Abstract: A semiconductor memory device with multi-bank structure, includes multiple voltage boosting circuits or internal power supply voltage generating circuits, each of which generates a high voltage to be provided to a bank. The respective voltage boosting circuits or internal power supply voltage generating circuits are sequentially selected under the control of a select signal generating circuit which generates select signals corresponding to the voltage boosting circuits by use of a row address strobe signal. According to the above-mentioned configuration, the number of the voltage boosting circuits is less than the number of banks in the memory device. Therefore, the area that the voltage boosting circuits or internal power supply voltage generating circuits occupy on a chip does not increase in proportion to the increase in the number of banks.

Abstract: A superscalar processor includes an execution unit that executes load/store instructions and an execution unit that executes arithmetic instruction. Execution pipelines for both execution units include a decode stage, a read stage that identify and read source operands for the instructions and an execution stage or stages performed in the execution units. For store instructions, reading store data from a register file is deferred until the store data is required for transfer to a memory system. This allows the store instructions to be decoded simultaneously with earlier instructions that generate the store data. A simple antidependency interlock uses a list of the register numbers identifying registers holding store data for pending store instructions.

Abstract: A video image frame consisting of a two-dimensional array of picture elements (pixels) is decomposed into a set of rectangular image portions (tiles). Within each tile, variance between pixel intensity values is less than a predetermined value. A tile is encoded by a value set identifying the tile and including a single intensity value for all pixels in the tile. Frame-to-frame variation of the video image is encoded by inter-frame tile comparison and encoding of sub-tiles representative of change from a previous frame to a current frame.

Abstract: A bipolar transistor in accordance with the invention includes a polysilicon base contact (607A) which is self-aligned with a polysilicon emitter (303). The polysilicon emitter is formed from a first polysilicon layer overlying an intrinsic base region (502) in a substrate (201). An extrinsic base (504) in the substrate is in contact with the intrinsic base and is self-aligned with a spacer (406) adjacent to the emitter. The polysilicon base contact is formed from a second polysilicon layer (407) in contact with the extrinsic base and overlying the emitter. A second sidewall spacer (508) is formed on the second polysilicon layer on step caused by the emitter. A protective layer (509, 510) formed on portions of the second polysilicon layer protects the base contact when the second spacer and the underlying portion of the second polysilicon layer are removed.

Abstract: Two dimensional data structures are represented by quadtree codes with embedded Walsh transform coefficients. The quadtree code permits both variable block size inherent in quadtrees, and the calculational simplicity of Walsh transform descriptions of nearly uniform blocks of data. Construction of the quadtree is calculationally simple for implementation in a digital system which does a bottom-up determination of the quadtree because Walsh transform coefficients and a measure of the distortion can be recursively calculated using only Walsh transform coefficients from the previous level in the quadtree. Uniform step size quantization, which is optimal for variable length coding and generalized gaussian distributions, permits fast encoding and decoding of quadtree code.

Abstract: A differential mode voltage controlled oscillator (VCO) includes an odd number of delay cells. Each delay cell has a pair of input terminals and a pair of output terminals with the input terminals of each delay cell being connected to the output terminals of a preceding delay cell in a ring. Each delay cell has a delay time for inverting a complementary pair of signals from which a clock signal is derived. A positive temperature coefficient voltage-to-current converter receives the control voltage of the VCO and controls the maximum currents (and therefore the delays) of the delay cells. A pair of cross-coupling transistors in each delay cell keeps the signals on the output terminals out of phase (complementary). The cross-coupling transistors have sizes which maximize gain of the delay cells at the threshold voltages of the cross-couple transistor and thereby increase output voltage swing at high frequencies.

Abstract: A process for forming field effect transistors having self-aligned source/drain contact includes: forming an gate overlying a portion of a semiconductor; forming a first sidewall spacer on the gate; forming a source/drain region in the semiconductor; depositing a conductive layer over the semiconductor so that a step is formed in the conductive layer in a region overlying the gate and the first sidewall spacer; forming a second sidewall spacer on the step; forming a protective layer over a portion of the conducting layer not covered by the second sidewall spacer; removing the second sidewall spacer to expose a portion of the conductive layer but leave covered a portion of the conductive layer underlying the protective layer; and removing the exposed portion of the conductive layer to leave a portion of the conductive layer in contact with the source/drain region and electrically isolated from the gate. The portion of the conductive layer left is the self-aligned contact.

Abstract: A leadframe for use in an integrated circuit package is described. The leadframe comprises a plurality of electrically conductive leads, a die attach pad, and an electrically conductive ring or rings formed generally around the circumference of the die attach pad and between the die attach pad and leads. In one embodiment, at least one of the leads is formed integrally with each ring. The die attach pad may also be formed integrally with one or more leads. In another embodiment, the ring or rings are formed so that they are electrically isolated from the die attach pad, and the die attach pad, leads, and ring or rings are all formed in substantially the same plane. In some embodiments, the ring or rings are broken into electrically isolated sections. Each of the ring sections (and die attach pad, if appropriate) may be electrically connected to a voltage source outside the integrated circuit package (e.g., a power supply or ground).