Abstract: A multiply unit uses four multipliers independently to perform for four parallel multiplications of single-width operands or uses the four multiplier cooperatively with an adder to perform a multiplication of double-width operands. In alternative embodiments, the adder operates in the same clock cycle as the multipliers or in a following clock cycle. Operand selection logic selects pairs of either single-width multiplicands or single-width partial multiplicands depending on for single or double-width multiplies.

Abstract: A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.

Abstract: Auto-tracking bit line reference schemes generate a “½ cell current” reference by programming reference cells to threshold voltages that are between threshold voltage levels used to represent data. A common word line can control both a selected memory cell and a reference cell to provide a reference current, and differential sense amplifiers can compare a bit line current to reference currents to thereby distinguish data values. Current through other reference cells can be mirrored to pull-up devices to further improve the tracking of the reference line and bit line currents. Embodiments of the invention can be used with binary and multiple-bit-per-cell memories and with a variety of memory array architectures and memory cell structures.

Abstract: A lamp device includes a power line and a light bulb socket connected to a light sensitive controller, and a rotary lamp base. The rotary lamp base includes a shell member, a tubular pivot seat, and a retaining unit. The shell member includes a top wall and a peripheral wall, and receives the socket and the controller therein. The top wall is formed with a through hole that has a hole axis. The peripheral wall is formed with a light sensor hole registered with the controller. The retaining unit retains rotatably a lower seat portion of the pivot seat in the through hole so as to permit rotation of the shell member relative to the pivot seat about the hole axis.

Abstract: A wavelet domain half-pixel motion compensation process that reduces aliasing effects that down sampling causes in the wavelet transform uses an H-transform and provides motion estimation and compensation in wavelet domain without requiring an inverse wavelet transform. For encoding, a q-dimensional (e.g., q=2) H-transform is applied in a conventional manner to non-overlapping q×q matrices in a first frame. When determining motion vectors for a second frame, “half-pixel” interpolation of the wavelet data of the first frame determines generates half-pixel data corresponding to q×q space-domain matrices that are offset (e.g., 1 pixel) horizontally and/or vertically from the q×q matrices that were transformed. Motion estimation techniques can then identify object motion by comparing wavelet domain object data in one frame to actual and interpolated wavelet domain data for another frame.

Abstract: Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming pulse width variation, and data-dependent bit line and/or source line biasing to achieve uniform programming accuracy across a range of target threshold voltages. A first type of write operations reaches different target threshold voltages during different time intervals, but uses word line signals that optimize threshold voltage resolution regardless of the target threshold voltage. A second type uses bit line and/or source line biases that depend on the multi-bit data values being written so that different memory cells reach different target threshold voltage at about the same time. Source line biasing can also reduce bit line leakage current through unselected memory cells during read or verify operations. A memory includes divided source lines that permit separate data-dependent source biasing.

Abstract: Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The conductive gate structure forms gates in device trenches in an active device region and forms a gate bus in a gate bus trench. The gate bus trench that connects to the device trenches can be wide to facilitate forming a gate contact to the gate bus, while the device trenches can be narrow to maximize device density. CMP process can be used to planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

Abstract: A multi-bit-per-cell non-volatile memory performs refresh operations that move data to different physical storage locations. The movement of data may extend the life of a non-volatile memory by avoiding repetitive erasing and writing of the same data value in the same memory cell. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In a particular embodiment, a refresh operation swaps the physical locations of two data blocks, and alternates between two mappings of physical addresses to logical addresses.

Abstract: A memory transistor has a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel. The memory transistor effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. The direction of the channel current controls which floating gate receives channel hot electron injection during programming and which floating gate state is sensed during reading. A read operation biases the word line higher that the threshold voltage used to store data and compares the resulting channel to reference currents to identify a stored binary, analog, or multi-bit value. The threshold voltage range can include negative threshold voltages, which increases the available range for multi-bit-per-floating gate storage.

Abstract: An electroplating process reduces the whisker formation rate that results from an interruption of the electroplating process for an alloy. The process forms a tin strike or a thin layer of a pure(>99.9%) metal on the alloy during an activation operation, so that an interruption in the electroplating process during which the lead frame or other work piece remains in an activation solution etches the pure metal layer rather than the alloy and thus does not unacceptably roughen the surface of the work piece. An exemplary embodiment forms a tin strike on a predominantly copper lead frame during an activation operation and forms an Sn—Pb solder layer on the tin strike during a plating operation. The solder layer is generally more than five times as thick as the tin strike layer.

Abstract: A flip-chip packaging method for a semiconductor device treats a portion of an interconnect substrate so that a fill material when liquid beads on the treated portion of the interconnect substrate. When the fill material is dispensed on the interconnect substrate to fill a gap under the semiconductor device, the beading of the fill material prevents formation of fillets that might otherwise create a variation in the thermal coefficient of expansion of fill material and/or warp the interconnect substrate. The treated portion of the interconnect substrate can be roughened or coated with a material that differs from other portions of the interconnect substrate and thereby causes beading.

Abstract: A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

Abstract: A multi-bit-per-cell non-volatile memory performs refresh operations that move data to different physical storage locations. The movement of data may extend the life of a non-volatile memory by avoiding repetitive erasing and writing of the same data value in the same memory cell. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In a particular embodiment, a refresh operation swaps the physical locations of two data blocks, and alternates between two mappings of physical addresses to logical addresses.

Abstract: A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

Abstract: A memory transistor has a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel. The memory transistor effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. The direction of the channel current controls which floating gate receives channel hot electron injection during programming and which floating gate state is sensed during reading. A read operation biases the word line higher that the threshold voltage used to store data and compares the resulting channel to reference currents to identify a stored binary, analog, or multi-bit value. The threshold voltage range can include negative threshold voltages, which increases the available range for multi-bit-per-floating gate storage.

Abstract: A flip-chip package uses a substrate having bond pad spacing that matches terminal spacing on a chip at an elevated temperature that is an expected operating temperature of the chip. The elevated temperature can be the midpoint of the desired temperature cycle of the chip so that deformations of the electrical connections in one direction balance deformations in the opposite direction during temperature cycling. Matching spacing at an elevated temperature, even a temperature less than the bonding temperature, permits a better alignment at the bonding temperature for formation of stronger bonds.

Abstract: A photo-ionization detector (PID) including two detection units controls gas flows through the ionization chambers of the detection units for real-time self-cleaning and measurement. Operation of the PID can include flowing gas through the ionization chamber of one detection unit to measure the volatile gas concentration while stopping gas flow through the ionization chamber of the other detection unit. A UV lamp converts oxygen contained in the closed ionization chamber to ozone, which removes contamination in the closed ionization chamber, Continuous gas flows can alternate between one ionization chamber to the other. Alternatively, a PID with only one gas detection unit intermittently interrupts the flow of the ambient gas in the ionization chamber.

Abstract: A method for time scale modification of a digital audio signal produces an output signal that is at a different playback rate, but at the same pitch, as the input signal. The method is an improved version of the synchronized overlap-and-add (SOLA) method, and overlaps sample blocks in the input signal with sample blocks in the output signal in order to compress the signal. Samples are overlapped at a location that produces the best possible output quality. A correlation function is calculated for each possible overlap lag, and the location producing the highest value of the function is chosen. The range of possible overlap lags is equal to the sum of the size of the two sample blocks. A computationally efficient method for calculating the correlation function computes a discrete frequency transform of the input and output sample blocks, calculates the correlation, and then performs an inverse frequency transform of the correlation function, which has a maximum at the optimal lag.

Abstract: A flip-chip package and packaging method use a substrate having bond pad spacing that matches terminal spacing on a chip at an elevated temperature, such as the temperature of the chip during bonding to the substrate, the melting point of solder used on the chip, a temperature within the range of thermal cycling of the chip, or an operating temperature of the chip. Matching spacing at an elevated temperature permits a better alignment at the bonding temperature for formation of stronger bonds.

Abstract: A gas analysis system and method use foreground broadband gas monitoring and background selective gas analysis. The foreground broadband monitoring indicates concentrations of a class of chemicals or contaminants in a gas sample, provides real-time warnings of contaminants, and can activate the background selective analysis. Separate broadband detectors and gas analyzers can respectively perform broadband monitoring and selective analysis. To reduce system components, a broadband detector that performs broadband monitoring switches to measure concentrations of chemicals output from a separation device for the selective analysis.