Abstract: A non-volatile, multi-bit-per-cell, Flash memory uses a storage process and/or architecture that is not sector-based. A data block can be stored without unused storage cells remaining in the last sector that stores part of the data block. For an operation erasing one or more data blocks, data blocks to be saved are read from an array and stored temporarily in a storage device. The entire array is then erased; after which the saved data blocks are rewritten in the memory with the amount of storage originally allocated to the erased data now being available for new data. This data arrangement does not subject any memory cells to a large accumulated cell disturbance because all data is read from the array and freshly re-written back into the array every time a record operation occurs. Additionally, the separate sectors in the memory device do not have different endurance histories that must be accounted for to extend the life of the memory.

Abstract: A Flash memory employs uniform-size blocks in array planes and has separate read and write paths connected to the array planes. The read path can read from one array plane while the write path writes in another array plane and one or more blocks are being erased. The uniform block size permits a symmetric layout and provides maximum flexibility in storage of data, code, and parameters. The uniform block size also allows spare blocks in the array planes to replace of any defective blocks. A redundancy system for the Flash memory uses a CAM and a RAM for address comparison and substitution to replace addresses corresponding to defective memory elements. To reduce access delays, part of the input address such as the row address goes directly to decoders, while another part of the input address such as the block address goes to the CAM array.

Abstract: A process for fabricating a BGA flip chip package containing a stiffener or heat spreader monitors edges of the adhesive that attaches the stiffener or heat spreader. The monitoring ensures that the adhesive extends beyond the centers of the outermost solder balls in the BGA. Stress at the edge of the adhesive thus does not cause warping or variations within the BGA.

Abstract: A contactless Flash memory has memory cells between each pair of adjacent diffused lines and about half as many metal lines as diffused lines. Bank select cells at the top of a bank in the memory connect the metal lines to pairs of diffused lines that are offset relative to pairs of diffused lines connected to the metal lines via bank select cells at the bottom of the bank. Decoding circuits activate the bank select cells at one end of a bank to access memory cells in odd-numbered columns of the bank and activate the bank select cells at the other end to access memory cells in even-numbered columns of the bank. For the access, all metal lines to one side of a selected memory cell are grounded, while all metal lines on the other side are biased for reading or programming of the selected memory cell.

Abstract: A manufacturing method for a multiple-bit-per-cell memory tests memory arrays in the memory and separately sets the number of bits stored per cell in each memory array. Memory arrays that testing proves are accurate when writing, storing, and reading a larger number of bits per cell are set to store more bits per cell, and memory arrays that cannot accurately write, store, or read as many bits per cell are set to store fewer bits per cell. The setting of the numbers of bits per cell for the respective memory arrays can maximize the memory capacity when some arrays perform better than expected. When the memory arrays perform worse than expected, the setting of the numbers of bits per cell can salvage the memory device even if the memory cannot provide the expected memory capacity.

Abstract: A video signal processor operates an arithmetic logic unit to perform on-the-fly compression of image data as the image data is input to the processor. The on-the-fly compression provides a data input pipeline that stores compressed image data for a large image area in a relatively small buffer in the processor. A hierarchical motion estimation process can first search the large image area by comparing blocks of the compressed image data to a compressed reference block. The hierarchical search process can then store uncompressed image data for a smaller image area and search the smaller image area to accurately determine a motion vector for the reference block.

Abstract: A multi-bit-per-cell memory reduces the effect of defects and data errors by scrambling data bits before writing data. The scrambling prevents storage of consecutive bits in the same memory cell. When a memory cell is defective or produces an error, the bits read from the memory cell do not create consecutive bit errors that would be noticeable or uncorrectable. An error or a defect in a multi-bit memory cell causes at most scattered bit errors. Scramblers in multi-bit-per-cell memories can include 1) hardwired lines crossing between an input port and an output port, 2) programmable wiring options, 3) a linear buffer where reads from the buffer use addresses with swapped bits, or 4) a buffer array that switches between incrementing a row address first and incrementing a column address first when accessing memory cells in the buffer array.

Abstract: A quantization circuit includes a set of prime number dividers that can be implemented as look-up tables and a shifter. A shifter implements divisions by prime number (two) and by powers of two. Multiplexing circuitry interconnects the prime number dividers to permit performance of a series of prime number divisions in a single clock cycle. The quantization circuit can thus implement one-cycle divisions by divisors that are products of the prime numbers and powers of two in the series that the multiplexing circuitry selects. For divisors that are longer series of the prime numbers implemented in the quantization circuit, the quantization circuit can implement multi-cycle divisions by feeding an output signal back through further series of the prime number dividers.

Abstract: A multi-bit-per-cell non-volatile memory performs refresh operations that move data to different physical storage locations. The movement of data may extend the life of a non-volatile memory by avoiding repetitive erasing and writing of the same data value in the same memory cell. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In particular embodiments, shifts sectors-sized data blocks cyclically among sectors in an array, a bank, or an entire memory or alternatively shifts the data blocks between two configurations.

Abstract: A contactless Flash memory uses a bank architecture with bank select devices and/or source line contacts at both ends of each bank. During programming, bank select devices at both ends of the bank supply currents to the memory cell being programmed, and/or diffused source lines conduct currents in both directions away from the memory cell being programmed. The multiple current paths reduce the current in any portion of the diffused lines and thereby reduce voltage drops in the diffused lines during programming. Accordingly, banks can have longer diffused lines (e.g., with twice as many cells per column of a bank) and still employ small bank select devices. The longer bank columns and smaller bank select devices result in an overall decrease in integrated circuit area for bank select devices, even though each bank has two bank select devices per diffused bit line.

Abstract: A multi-bit-per-cell non-volatile memory stores different portions of a data stream using different numbers of bits per cell. In particular, data that requires a high degree of data integrity (e.g., the header of a data frame) is stored using a relatively small number of bits per memory cell. Data that is more error-tolerant (e.g., the main data representing music, images, or video) is stored using a relatively large number of bits per memory cell. Write circuitry decodes an input data stream and determines the number of bits to be written in each memory cell. Read circuitry decodes an output data stream and determines a number of bits read from each memory cell to generate the data stream. One such memory includes a decoder in the write circuitry and a decoder in the read circuitry, and another embodiment includes a single decoder that the write and read circuits share.

Abstract: A non-contact holder including one or more chucks holds a planar workpiece such as a semiconductor wafer, particularly a thin wafer. Each chuck in the holder includes a cavity that opens to a surface adjacent to the workpiece. A tangential orifice introduces a tangential gas flow into the cavity to create a vortex having a central, low-pressure region. A central orifice directs a gas flow into the low-pressure region of the vortex. The combination of gas flows creates a more uniform vacuum attraction holding a workpiece in close proximity to the chuck. The gas exiting from the chuck provides a cushion that prevents contact between wafer and chuck. Small diameter chucks located close to each other help avoid distortion when processing very thin workpieces. In addition to equalizing pressure, the central gas flow increases the angular spread of gas exiting from each chuck and thus simplifies the design of a holder providing a gas flow that inhibits entry of contaminants between the holder and the workpiece.

Abstract: A plasma apparatus separately measures multiple plasma jets upstream of where the plasma jets converge into a combined plasma stream. The separate plasma jets can be separately adjusted to place the separate jets in a configuration that provides the combined stream with desired properties for a plasma treatment. The system can include an injector for a neutral jet that becomes part of the combined plasma stream. With an injector, the positions of the plasma jets can be measured relative to the injector so that the plasma jets and the neutral jet are properly aligned to form a combine plasma stream having the properties desired.

Abstract: A video processor has motion estimation, pixel processing, and general processing modes. In the processor, an internal memory acts as a buffer containing a search window in motion estimation mode and as a scratch pad in pixel and general processing modes. Another internal memory acts as a buffer for a reference block in search mode and as a register file in pixel and general processing modes. Both internal memories provide parallel pixel-size data elements in pixel processing mode and larger data elements in general processing mode. An ALU in the processor has multiple slices that operate independently for parallel processing in motion estimation and pixel processing modes and cooperatively to provide a larger data width for general purpose processing mode.

Abstract: A multi-bit-per-cell non-volatile memory periodically reads and rewrites data and thereby refreshes threshold voltages and removes the effects of threshold voltage drift. Accordingly, threshold voltages are kept in narrower ranges, and the narrow ranges allow more distinct levels for data values and allows storage of more bits per cell. A refresh interval is according to the size of windows for different multi-bit values and the measured or expected rate of threshold voltage drift. An on-chip refresh timer and arbitration logic selects when to initiate a refresh operation. A refresh can use a data buffer for temporary storage or can directly write data from one memory location to another. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In particular embodiments, shifts sectors-sized data blocks cyclically among sectors in an array, a bank, or an entire memory or alternatively shifts the data blocks between two configurations.

Abstract: A multiple-bit-per-cell memory includes multiple memory arrays, where the number of bits stored per cell is separately set for each of the memory arrays. Memory arrays that testing proves are accurate when writing, storing, and reading a larger number of bits per cell are set to store more bits per cell, and memory arrays that cannot accurately write, store, or read as many bits per cell are set to store fewer bits per cell. Accordingly, the setting of the numbers of bits per cell for the respective memory arrays can maximize the capacity of a memory when some arrays perform better than expected. When the memory arrays on average perform worse than expected, the setting of the numbers of bits per cell salvage the memory device even if the memory is unable to provide the total expected memory capacity. One implementation of the memory includes a register for the settings of the memory arrays and one or more analog/multi-level write and read circuits.

Abstract: A multi-level non-volatile memory includes one or more arrays of memory cells including storage cells and dummy cells. The memory observes or measures write operations that write dummy values to the dummy cells and from the observations or measurements selects parameters such as programming voltages or the duration of program cycles. The selection of parameters optimizes write precision within the available access time of a high bandwidth memory. Accessing dummy cells also allows the memory to reach a steady state before writing or reading of data begins. In particular, multiple pipelines sequentially start write operations, and writing of data begins when an equilibrium number of pipelines are performing write operations. Similarly, multiple read operation start before the reading of data for actual use. The stabilization is particularly critical when the pipelines share a power source.

Abstract: A multi-level non-volatile memory includes one or more arrays of memory cells including storage cells and dummy cells. The memory observes or measures write operations that write dummy values to the dummy cells and from the observations or measurements selects parameters such as programming voltages or the duration of program cycles. The selection of parameters optimizes write precision within the available access time of a high bandwidth memory. Accessing dummy cells also allows the memory to reach a steady state before writing or reading of data begins. In particular, multiple pipelines sequentially start write operations, and writing of data begins when an equilibrium number of pipelines are performing write operations. Similarly, multiple read operation start before the reading of data for actual use. The stabilization is particularly critical when the pipelines share a power source.

Abstract: Image data is processed by identifying a region of substantially constant color within a first image. Color variations, in terms of standard deviation about an average color, are analyzed and a similar level of variation is applied to a second image. The first image may be derived from cinematographic film, with color variations due to film grain. The second image may be a video image or a computer generated image and the application of a similar level of variation may reproduce noise similar to that present within the film due to grain. In this way, it is possible to add grain to non-filmed images so as to match said images to images derived from film.

Abstract: A read operation for a multi-level or a multi-bit-per-cell non-volatile memory biases a selected row line cell at a fixed voltage that is above the maximum possible threshold voltage representing data and changes the column line load for a selected column line. The column line load that corresponds to the trip-point of a sense amplifier indicates the data stored in the memory cell coupled to the selected row and column lines. A corresponding write process uses the same fixed row line voltage for both program and verify cycles. The programming voltage can be the same as the row line voltage for the read operation or can depend on the data value being written. To better control programming, the duration of the program cycles and/or the load on the drain or source of the selected memory cell during a program cycle varies with time and depends on the value being written. One memory in accordance with the invention includes variable column line loads for use during read and write operations.