Patents Represented by Attorney, Agent or Law Firm Edward C. Kwok
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Patent number: 6650265Abstract: A method and circuit structure scale the power consumption of a current mode digital/analog converter (DAC) in proportion to performance parameters, such as sampling speed (i.e., clock samples per second) and resolution (number of bits) under programmable control. In one embodiment, a current mode segmented DAC provided approaches the performance of custom implementations designed for specific combinations of these parameters, across a wide range of such parameters by varying current relative to the sampling rate and the resolution and by selectively enabling current sources in the DAC.Type: GrantFiled: April 25, 2002Date of Patent: November 18, 2003Assignee: Engim, Inc.Inventor: Alexander Bugeja
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Patent number: 6646343Abstract: A method and an integrated circuit package support a high-speed integrated circuit operating at 10 GHz or higher switching speeds. The packaged integrated circuit has external terminals, a semiconductor die having conventional bonding pads, a substrate (e.g., printed circuit board) having conductive traces to couple input, output or bi-directional signals between bonding finger areas of the conductive traces and the external terminals. A ground plate that is electrically isolated from a conductive trace is positioned in the vicinity of the bonding finger area of the conductive trace. Bond wires connect the bonding pads of the electronic circuit and the bonding finger areas of the conductive traces. The ground plate improves integrity in a high-speed signal by canceling the complex impedance of a bond wire.Type: GrantFiled: June 14, 2002Date of Patent: November 11, 2003Assignee: BitBlitz Communications, Inc.Inventors: Nirmal Sharma, Ge Gong, Jason Chen
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Patent number: 6643831Abstract: A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.Type: GrantFiled: January 24, 2002Date of Patent: November 4, 2003Assignee: Sequence Design, Inc.Inventors: Keh-Jeng Chang, Li-Fu Chang, Robert G. Mathews, Martin G. Walker
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Patent number: 6621439Abstract: A method for implementing segmented digital-analog converters (DACs) operating in the current mode matches the time constants in the most-significant-bit (MSB) segments to the time constants in the (LSB) least-significant-bit segments, and any intermediate-significant-bit (ISB) segments. The method can be implemented using the simple addition of capacitances or the resizing of transistors in the circuit at appropriate points. The resulting DAC exhibits high dynamic linearity and spurious free dynamic range (SFDR).Type: GrantFiled: April 25, 2002Date of Patent: September 16, 2003Assignee: Engim, Inc.Inventor: Alexander Bugeja
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Patent number: 6598209Abstract: A system for analyzing the power consumption of a behavior description of an electrical design includes a structural element library including a set of technology-independent structural macro elements, a macro power model module providing macro power models for one or more of the structural macro elements in the structural element library, and a power estimation module providing a power consumption value of the electrical design using a netlist of interconnected components representative of the electrical design, and the macro power models. The macro power models are associated with corresponding power models in a user-specified gate-level power model library. The power analysis system enables behavior level or RTL power analysis using a user-specified gate-level cell power model library containing arc-based or pin-based power model descriptions or both.Type: GrantFiled: February 28, 2001Date of Patent: July 22, 2003Assignee: Sequence Design, Inc.Inventor: Serguei A. Sokolov
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Patent number: 6594576Abstract: A system and a method for determining and disseminating current traffic information is presented. A traffic data compilation computer linked to a data network collects location data from mobile units, each of which is associated with an identification number. The computer compiles the location data, calculates the velocity of each mobile unit, compares the velocity of each mobile unit against speed limit data stored in a memory, and stores the difference. The traffic data compilation computer determines the traffic condition based on the difference between the velocity of each mobile unit and the speed limit. In addition, traffic data compilation computer may determine the fastest route between point A and point B under the current traffic conditions. Traffic data compilation computer determines the possible routes between point A and point B, retrieves the velocity data from a database, and derives the estimated travel time for each of the possible routes.Type: GrantFiled: July 3, 2001Date of Patent: July 15, 2003Assignee: At Road, Inc.Inventors: Rodric C. Fan, Xinnong Yang, James D. Fay
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Patent number: 6591407Abstract: A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.Type: GrantFiled: March 1, 2000Date of Patent: July 8, 2003Assignee: Sequence Design, Inc.Inventors: Douglas Kaufman, Hazem Almusa, Vinay Srinivas, Donald V. Organ, Larry Ke, Wei Li, Japinder Singh, Robert Mathews
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Patent number: 6574787Abstract: An embodiment of the present invention is a method for logic synthesis that reduces use of computer memory and reduces computer runtime. In particular, an embodiment of the present invention is a method for logic synthesis which includes the steps of: (a) analyzing an HDL model to develop a parse tree and (b) elaborating the parse tree to create a word-oriented netlist.Type: GrantFiled: August 16, 1999Date of Patent: June 3, 2003Assignee: Sequence Design, Inc.Inventor: Glen R. Anderson
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Patent number: 6552682Abstract: A method for distributing locating-relevant information includes providing a GPS position of a client to a server on a data network, and returning location-relevant information by the server based on the specified GPS position. Such location-relevant information include travel or tourist information (e.g., locations of tourist attractions, hotels, or restaurants). Commercial information such as discount coupons or advertising selected based on the Client's GPS position can also be provided. Financial or business transactions can be conducted using the GPS position for authentication or identification.Type: GrantFiled: October 20, 1999Date of Patent: April 22, 2003Assignee: At Road, Inc.Inventor: Rodric C. Fan
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Patent number: 6542116Abstract: To determine the clock doppler of a signal receiver, sampled data received from a receiver into are divided into data segments of incremental length. The clock doppler is estimated based on correlating each data segment with the expected signal from each satellite, from a set of satellites, that is overhead the receiver. For each data segment, the correlated result of each satellite is used to refine subsequent calculations of the clock doppler of the next overhead satellite. When the clock doppler calculations for a data segment have been performed using all overhead satellites from the set of satellites, then the results for that data segment are used to refine the calculations for the next data segment.Type: GrantFiled: June 22, 2001Date of Patent: April 1, 2003Assignee: Enuvis, Inc.Inventors: Anant Sahai, Andrew Chou, Wallace Mann, Stefano Casadei
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Patent number: 6535163Abstract: To determine the location of a signal receiver, sampled data received from a receiver is divided into data segments of increasing length. Current ranges for a delay value and for a modulation frequency value are calculated relative to each satellite signal source that is overhead the signal receiver. Using the data segments of increasing length, the current ranges, estimates for the delay value and for the modulation frequency value are then iteratively calculated and updated. For each signal source, I and Q correlation integrals and their magnitude values are calculated using the modulation frequency value estimate and each of a range of delay values centered around the delay value estimate. The resulting magnitude-curve is interpolated using the calculated magnitude values. The location of the receiver is calculated using the shape of the magnitude-curve to represent the I and Q correlation integrals for each signal source.Type: GrantFiled: June 22, 2001Date of Patent: March 18, 2003Assignee: Enuvis, Inc.Inventors: Anant Sahai, John Tsitsiklis, Benjamin Van Roy, Andrew Chou, Wallace Mann, Jesse Robert Stone, Wungkum Fong
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Patent number: 6529159Abstract: A method for distributing locating-relevant information includes providing a GPS position of a client to a server on a data network, and returning location-relevant information by the server based on the specified GPS position. Such location-relevant information include travel or tourist information (e.g., locations of tourist attractions, hotels, or restaurants). Commercial information such as discount coupons or advertising selected based on the Client's GPS position can also be provided. Financial or business transactions can be conducted using the GPS position for authentication or identification.Type: GrantFiled: March 8, 2000Date of Patent: March 4, 2003Assignee: At Road, Inc.Inventors: Rodric C. Fan, Amin Mufti
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Patent number: 6525688Abstract: Some embodiments of the invention provide a location-determination system that includes several transmitters and at least one receiver. Each transmitter transmits a signal that includes a unique periodically-repeating component, and the receiver receives a reference signal. Based on the received reference signal, the location-determination system identifies an estimated location of the receiver as follows. For each transmitter in a set of transmitters, the system computes a phase offset between the received reference signal and a replica of the transmitter's periodically-repeating component. The system also identifies an approximate location of the receiver and an approximate receive time for the received signal. The system then uses the identified approximate location and time, and the computed phase offsets, to compute pseudoranges for the set of transmitters. Finally, the system identifies the estimated location of the receiver by using the computed pseudoranges.Type: GrantFiled: June 20, 2001Date of Patent: February 25, 2003Assignee: Enuvis, Inc.Inventors: Andrew Chou, Benjamin Van Roy, John Tsitsiklis
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Patent number: 6525687Abstract: Some embodiments of the invention provide a location-determination system that includes a number of transmitters and at least one receiver. Based on a reference signal received by the receiver, this location-determination system identifies an estimated location of the receiver within a region. In some embodiments, the system selects one or more locations within the region. For each particular selected location, the system calculates a metric value that quantifies the similarity between the received signal and the signal that the receiver could expect to receive at the particular location, in the absence or presence of interference. Based on the calculated metric value or values, the system identifies the estimated location of the receiver.Type: GrantFiled: February 12, 2001Date of Patent: February 25, 2003Assignee: Enuvis, Inc.Inventors: Benjamin Van Roy, John Tsitsiklis, Andrew Chou
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Patent number: 6519755Abstract: An embodiment of the present invention is a method for logic synthesis that reduces use of computer memory and reduces computer runtime. In particular, an embodiment of the present invention is a method for logic synthesis which includes the steps of: (a) analyzing an HDL model to develop a parse tree and (b) elaborating the parse tree to create a word-oriented netlist; wherein elaborating comprises word-oriented elaborating.Type: GrantFiled: August 16, 1999Date of Patent: February 11, 2003Assignee: Sequence Design, Inc.Inventor: Glen R. Anderson
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Patent number: 6512479Abstract: Techniques are provided for aiding in acquiring a signal using the data bit information that is associated with each signal source. One aspect of the invention is to use the data bit information that is associated with each signal source when calculating the In Phase and Quadrature correlation integrals by using the sampled data associated with the received signal. By using the data bit information that is associated with each signal source, coherent correlation may be performed by breaking the signal into data blocks and performing calculations on a block-by-block basis. Coherent correlation is the calculation of In Phase and Quadrature correlation integrals for sampled data that is associated with the received signal.Type: GrantFiled: June 22, 2001Date of Patent: January 28, 2003Assignee: Enuvis, Inc.Inventors: Anant Sahai, Wallace Mann, Andrew Chou, Benjamin Van Roy
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Patent number: 6493648Abstract: An embodiment of the present invention is a method for logic synthesis that reduces use of computer memory and reduces computer runtime. In particular, an embodiment of the present invention is a method for logic synthesis which includes the steps of: (a) analyzing an HDL model to develop a parse tree; (b) elaborating the parse tree to create a word-oriented netlist; and (c) inferring complex components from the word-oriented netlist.Type: GrantFiled: August 16, 1999Date of Patent: December 10, 2002Assignee: Sequence Design, Inc.Inventor: Glen R. Anderson
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Patent number: 6487527Abstract: A linear predictive speech encoding method combines vector quantization with the search for roots of LSP polynomials. At Under this method, a code book searchable using line spectral pair (LSP) values is created from a line spectral frequency (LSF) code book, thus ensuring linear distortion performance without the costly run-time complexity of finding roots to high-order LSP polynomials in the LSF domain.Type: GrantFiled: May 9, 2000Date of Patent: November 26, 2002Assignee: Seda Solutions Corp.Inventor: Rahmin Soheili
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Patent number: 6459988Abstract: A method and a system using the Global Positioning System (GPS) to detect and report vehicle accidents are presented. GPS, which is currently used primarily for vehicle positioning, can be combined with wireless technology to automatically report accidents to third parties. A mobile unit placed or installed in a vehicle receives code sequences from the GPS satellites, converts the code sequences to positional information, and transmits the positional information to a server. The server derives the acceleration of the mobile unit from the positional information and compares the acceleration with a threshold value. In one embodiment, a microprocessor included in the mobile unit derives the acceleration and compares the acceleration with a threshold value. The threshold value represents acceleration that can be achieved only with an external force such as a collision.Type: GrantFiled: June 12, 2001Date of Patent: October 1, 2002Assignee: At Road, Inc.Inventors: Rodric C. Fan, Carey B. Fan, David Mleczko
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Patent number: 6417848Abstract: A 3-D graphics system combines a software programmed setup processor, a 3-D pipeline, and a software programmed back end processor. The setup processor performs “setup” on polygons for the 3-D pipeline. The 3-D pipeline rasterizes the polygons to create pixels. The back end processor performs back end processing, such as Z-buffering and alpha blending on the pixels. In one embodiment, the throughput of the 3-D graphics system is increased by clusterizing the pixels before back end processing. Specifically, a clusterizer combines pixels into clusters that can be processed by the back end processors without data coherency problems. Furthermore, the pixels are selected for a cluster to minimize memory latency and access times. In some embodiments, clusters are filled with fill addresses by a cluster filler. The filled addresses generated by the cluster filler, do not cause potential hazards in the back end processor.Type: GrantFiled: August 25, 1997Date of Patent: July 9, 2002Assignee: ATI International SRLInventor: James T. Battle