Abstract: An adder tree includes several partial product generators, each generating a bit of equal weight. An adder receives the bits and provides a carry bit to a logic unit. The logic unit propagates the carry bit to the next more significant column in response to a carry enable instruction. The logic unit outputs a bit that is independent of the carry bit in response to a lack of a carry enable instruction.

Abstract: A current source for providing matched currents at low and variable bias voltages. The current source includes a first circuit, a second circuit, and a biasing circuit. The first circuit provides a first current. The first circuit includes a first transistor with a control terminal, a first terminal, and second terminal. A second circuit provides an output current to an output node. The second circuit includes a second transistor with a control terminal, a first terminal, and second terminal. The biasing circuit includes a third transistor with a control terminal, a first terminal, and second terminal. The biasing circuit also includes a fourth transistor with a control terminal, a first terminal, and second terminal. The biasing circuit provides a voltage at the first terminal of the third transistor and a voltage at the control terminal of the second transistor so that a voltage at the first terminal of the second transistor and a voltage at the second terminal of the first transistor match.

Abstract: A programming and erase method that extends erase time degradation of nonvolatile memory devices by using a constant erase voltage and a set of program voltages, where the average program voltage of the set of the program voltages is approximately equal to the constant erase voltage.

Abstract: An erase control circuit erases a memory cell in accordance to an erase signal value that can be varied by a test equipment. The erase control circuit comprises a signal storage device, a signal output circuit, and a verification circuit. The signal storage device stores the erase signal value. A test equipment can be coupled to the signal storage device to write the programming signal value into the signal storage device. The signal output circuit is coupled to the signal storage device to receive the erase signal value. The signal output circuit converts the erase signal value into an erase signal and outputs the erase signal to the memory cell. The verification circuit determines whether the memory cell is successfully erased. If the memory cell is not successfully erased, the erase control circuit increases the erase signal value.

Abstract: An active pixel sensor including low threshold voltage transistors advantageously provides an increased output swing over an active pixel sensor of the prior art. The low threshold voltage transistor can be achieved using either a native transistor or a depletion mode transistor. In a process in which a threshold adjustment implant step is separately masked, the active pixel sensor of the present invention can be manufactured with no additional masking requirements. In one embodiment, a low threshold voltage (VTN) allows a transistor acting as a reset switch to operate in the linear region, and allowing the reset switch transistor to share a common supply voltage source with a readout amplifier transistor.

Abstract: Leadless plastic chip carriers are formed from a matrix of lead frames provided in a section of a metal strip. Each lead frame in the matrix includes a die-attach pad and multiple leads disposed in close proximity to the die-attach pad. After a semiconductor die is attached to each of the die-attach pad and wire-bonded, the leadless plastic chip carriers are formed by providing a plastic encapsulation which exposes the bottom sides of the die-attach pad and the leads. The bottom sides of the leads serve as solder pads to be used for attaching the leadless plastic chip carrier to a printed circuit board.

Abstract: A virtual world computer process includes portable virtual token objects that can be used by on-line users of the virtual world to facilitate exchange of goods and services within the virtual world. In particular, client-server computer processes are provided for the virtual world that allow on-line users to conduct activities within the virtual world including getting, putting, giving, and receiving portable virtual token objects as well as other portable virtual objects. Each on-line user is represented in the graphic user interface by a virtual avatar object. Token objects are put into circulation by virtual ATM objects. A virtual ATM object allows a user to obtain a balance, deposit tokens, and withdraw tokens. A vendroid object is an object that sells portable virtual items in exchange for tokens deposited by avatars. Different virtual items have different values, and vendroids do not all have the same virtual items for sale. In the virtual world, a lurker is represented in a locale by a ghost object.

Abstract: A circuit for providing hi-Z charging of a deeply discharged battery includes a load simulator circuit to provide a charging load resistance even when the battery has been discharged to 0V. The load simulator circuit includes a transistor connected in series with the battery. A logic circuit detects when the battery voltage is below a minimum threshold voltage and instructs a voltage control circuit to provide a constant voltage across the battery and the load simulator circuit. The logic circuit also applies the output of a current control circuit to the gate terminal of the transistor, enabling the current control circuit to regulate the total resistive load of the battery-transistor pair and thus maintain a constant hi-Z charge current across the battery.

Abstract: The present invention provides an improved interpreter for stack-based languages. In one embodiment, a method includes executing a first interpreter for a first state, and executing a second interpreter for a second state. In particular, the first state indicates that no elements of a stack are stored in registers of a microprocessor, and a second state indicates that an element of the stack is stored in a register of the microprocessor.

Abstract: A floating point arithmetic logic unit includes two rounding units that select between an incremented, unincremented, and complemented result from a carry propagate adder. A fast rounding unit selects a result as an approximation based on the equality or inequality of the exponents of the operands, the relative sizes of the mantissas and the presence of a guard bit. The result selected by the fast rounding unit is received by a leading zero count unit, which counts the leading zeros of the result. A second slower rounding unit meanwhile makes a selection between the incremented, unincremented, and complemented results based on the rounding mode, the sign of the result and whether the result is exact. The result is inexact when both the most significant bit and the guard bit are equal to one. While the slower rounding unit may take longer to determine the appropriate selection, the result selected is the most accurate.

Abstract: A bipolar analog multiplier with a greatly reduced output sensitivity to temperature. The multiplier uses the difference between the multiplier input voltages and the reference voltages to generate currents. Voltages which are logarithmically dependent on the generated currents are developed and applied to inputs of bipolar variable transconductance stages. Circuits are used to reduce ringing at the output of the multiplier.

Abstract: A floating point unit includes a rounding unit that rounds the two least significant bits of a sum. After a sum of the two mantissas is generated the at least one least significant bit is separated from the sum. When addition is performed, two least significant bits are separated from the sum. A half add unit may be used to generate the sum along with a set of carry data, and thus at least one least significant bit of the carry data is also separated. A rounding unit receives the separated at least one least significant bit of the sum and carry data and produces a carry in bit as well as rounded at least one least significant bit. The sum and carry data are then summed in a later stage of the floating point unit to form both a unincremented sum and an incremented sum, which are stored in a multiplexer. The carry in bit is used to select one of the unincremented sum and incremented sum.

Abstract: A double incrementing adder includes an AND gate configured to receive bits of the two input values of a common weight (“first weight”). The AND gate has an output terminal configured to carry the AND'ed bit. A three input XOR gate is configured to receive bits of the two input values of a common weight (“second weight”) one bit more significant than the first weight. The three input XOR gate is configured to XOR these values with the AND'ed bit to generate a three input XOR'ed bit.

Abstract: A channel region is formed in a device after the source and drain regions are formed by implanting ions into the channel region with a tilt angle using multiple rotations. A rapid thermal annealing step is performed to activate the channel dopant. Because the source and drain regions are already formed, a relatively low temperature, e.g., 990 to 1010 degrees Celsius, and short, e.g., 1 to 5 seconds, rapid thermal annealing step may be performed to activate the channel region. Thus, the dopant concentration in the channel region may be well localized and accurately controlled.

Abstract: An input structure protects an Integrated Circuit (IC) against increases in the IC pad voltage when the supply voltage to the IC is tuned off. The input structure includes circuitry for transferring either a divided-down pad voltage or the positive supply voltage to a buffer circuitry. The buffer circuitry receives the voltage transferred thereto and lowers the pad voltage. The lowered pad voltage generated by the buffer circuitry is subsequently applied to the IC.

Abstract: The invention provides a method and apparatus for enhancing apparent image resolution by way of multi-line interpolation.

Abstract: A time-multiplexed common mode feedback circuit provides a common mode feedback signal during active phases of a clock signal. The common mode feed back circuit includes capacitors which are charged during the inactive phases of the clock signals. In one embodiment, the common mode feedback signal is provided by two generator circuits each driven by a respective one of two non-overlapping clock signals. In that embodiment, the generator circuits provide the common mode feedback signal during the active phases of their respective clock signals.

Abstract: An improved deinterlacing technique is provided. In one embodiment, a method for deinterlacing includes receiving an interlaced frame of data, the frame including a primary field and a secondary field, and deinterlacing the frame, the deinterlacing including computing an output pixel, PIXOUT, of the secondary field based on an input pixel, PIXIN, of the secondary field, a bottom pixel, BOTTOM, of the primary field, and a top pixel, TOP, of the primary field, in which PIXOUT is computed according to an input/output curve that converges to an average of BOTTOM and TOP. The deinterlacing technique in accordance with this embodiment minimizes spatial artifacts and efficiently generates each output pixel value from only three input pixels.

Abstract: A system for raising a person lying on the ground includes a lifting seat 10 comprising a back rest 12 coupled to a seat portion 18. At either side of the back rest 12 and seat portion 18 there are provided side supports 14, 16, 20 and 22. The system is such that in use it can be slid onto a person lying on his/her side, rotated such that the back rest 12 lies on the ground, with the supports 14-22 supporting the person during rotation to a back-lying position. The back rest 12 can then be rotated upwardly to bring the person into a sitting position.