Abstract: A method for minimizing instantaneous currents ina signal bus is disclosed. The method involves providing a programmable delay element in each of the signal buffers driving the signal on the bus. The programmable delay element in each signal buffer is selectable enabled to include a predetermined time delay. The method involves programming the delay elements in a selected group of the signal buffers t includde the predetermined time delay, so that the selected group of signal buffers each generate an output signal switching after the predetermined delay relative to the switching of output signals generated by other signal buffers.

Abstract: A method for removing a resistive film formed on an electrode to increase the conductive contact area of the electrode positioned in a misaligned contact hole. The method comprises providing a substrate supporting an electrode layer. The electrode layer is etched to produce metal lines. During the processing of the metal lines, a resistive film is formed thereon. The resistive film is removed and a protective barrier is formed on the metal lines. A dielectric layer is formed on the substrate, including the metal lines. The dielectric layer is subsequently patterned to form contact holes or vias to expose a portion of the metal lines. The contact holes are filled with plugs such that a second electrode layer can be formed on the dielectric layer and the plugs.

Abstract: A wireless data network, including a base station and multiple mobile wireless terminals, implements a synchronous 2-way communication protocol in which the availability of a communication channel is signalled by the base station in a control packet. The multiple mobile wireless terminals compete for acquisition of the communication channel by sending a request packet, upon detecting from the control packet that the communication channel is available. The base station grants the channel by acknowledging the request packet of a selected one of the mobile wireless data terminal. The mobile wireless data terminal communicates with the base station over the communication channel subsequent to acquisition. Upon the wireless data terminal relinquishing the communication channel, the base station sends out the next control packet indicating that the communication channel is again available.

Abstract: A method for fabricating copper-aluminum metallization utilizing the technique of electroless copper deposition is described. The method provides a self-encapsulated copper-aluminum metallization structure.

Abstract: A client-server network management system includes: a plurality of managed computer network elements, a managed element server that executes on a first computer; and at least one managed element server client that typically executes on a second computer. The managed element server and managed element server client are computer processes that execute from memory of their respective computers. The client-server network management system is really two applications in one: a visual element manager builder and a manager. The manager provides the run-time environment in which element managers are executed to monitor and manage computer network behavior such as network throughput, collision rate, and number of duplicate IP packets, to name a few. The manager portion of managed element server is independent of any graphic user interface. The logic and structure of the manager of managed element server is cleanly separated from the graphic user interfaces.

Abstract: An improved wafer polishing machine is disclosed. In one embodiment, the wafer polishing machine has a movable polishing surface and a holder that holds an object, such as a semiconductor wafer, against the movable polishing surface. The holder includes a support structure that supports the object in contact with the polishing surface and an annular retaining ring that retains the object in alignment with the support structure. The retaining ring has a plurality of projections projecting inwardly from its inner circumference. The projections are evenly spaced around the inner circumference of the retaining ring. In one embodiment, the projections on the retaining ring define a circle with a diameter no less than the diameter of the object being polished. In an alternative embodiment, the retaining ring has a smooth, circular inner circumference formed from a flexible material which distends to from a continuous arc of contact with the wafer during polishing.

Abstract: A memory system has the capability to adjust a program or erase voltage if the time to program or erase is excessive. The memory system comprises at least a memory cell, a voltage value storage device, a voltage source, and a voltage adjustment circuit. The voltage value storage device stores a voltage value. The voltage source receives and converts the voltage value into a voltage. The voltage source applies the voltage to at least one memory cell. The voltage adjustment circuit is also coupled to receive the stored voltage value. The voltage adjustment circuit determines the time required to program or erase at least one memory cell using the voltage value. If the time to program or erase at least one memory cell is excessive, the voltage adjustment circuit increments the voltage value stored in the voltage value storage device.

Abstract: In a SOI structure according to the invention, a substrate region directly adjacent and underlying the buried oxide layer is doped with a dopant having a conductivity type opposite that of the substrate. This produces a junction between the doped layer and the substrate. Appropriately biasing this junction creates a depletion layer, which effectively extends the width of the buried oxide layer deep into the substrate, thereby reducing parasitic capacitance in the SOI structure, particularly for inductors, interconnects, and other passive circuit elements. Reducing parasitic capacitance reduces associated substrate losses and RC propagation delays. These benefits become increasingly important at high frequencies encountered in RF wireless communication and high speed digital applications.

Abstract: A video pre-amplifier includes an input stage and an output stage. In one embodiment, an on-screen display signal is provided to the output stage, and a control signal is asserted when the on-screen display signal is active. With respect to a video output signal, both the gains of the input stage and output stage are adjusted when the control signal is asserted. In one embodiment, the control signal is generated by a comparator within the output stage.

Abstract: A method for routing clock signals in an integrated circuit provides a hierarchical routing scheme in which the lowest level clock buffers are first placed row by row in preallocated locations and routed to the input pins of standard cells receiving the output clock signals of these clock buffers. Under the method, the number of clock buffers to be placed in each row is computed according to estimates of their load capacitances and expected wiring lengths within a window. The output buffers of the same clock signal are gridded or strapped together to minimize clock skew. A second level of clock buffers are then assigned to drive the lowest level buffers. The hierarchy can be extended to any number of higher levels, until clock signals are routed for the entire integrated circuit. The higher level clock signals can also be strapped or gridded to minimize clock skew.

Abstract: The present invention provides a two-port memory to connect a microprocessor bus to multiple peripherals. In one embodiment, an apparatus for an IO gateway subsystem of a microprocessor includes a bus of the microprocessor connected to a two-port memory, and a first peripheral connected to the two-port memory and a second peripheral connected to the two-port memory. In particular, the two-port memory communicates with the bus at a first clock rate, the two-port memory communicates with the first peripheral at a second clock rate, and the two-port memory communicates with the second peripheral at a third clock rate, in which the first clock rate, the second clock rate, and the third clock rate are asynchronous (e.g., the clocks have different phases, or the clocks have different frequencies).

Abstract: A capacitor divider includes two capacitors coupled in series between two voltage sources. A first capacitor is a floating gate capacitor having one plate being the control gate of a floating gate transistor structure and the other plate being a source, drain, and channel region of the floating gate transistor structure. The capacitive divider has the advantage of having at least one floating gate capacitor, can be implemented in a voltage regulator, and works for a variety of voltages across the capacitors.

Abstract: A dual damascene process and structure for fabricating semiconductor devices are disclosed. In one embodiment of the invention, a protection layer is deposited on top of a metal layer to protect the metal layer during subsequent etching of an oxide layer to form the via and damascene trench. Because the selectivity between the oxide layer and the protection layer is high, the number and complexity of processing steps are thereby reduced. Other embodiments of the present invention use a metal sealant layer and/or anti-reflective coating in conjunction with the protection layer in a dual-damascene process.

Abstract: A squaring circuit includes an input terminal that carries a k-bit input value. The k-bit input value has left m-bit and right (k−m)-bit portions representing respective left and right hand values. A left hand squaring circuit receives the left hand m-bit portion and generates a first term bit group representing a square of the left hand value. A multiplier multiplies the left hand m-bit portion and the right hand (k−m)-bit portion to generate a second term bit group representing a product of the left and right hand values. A right hand squaring circuit generates a third term bit group representing a square of the right hand value. An adder adds the second term bit group with a concatenation of the first and third term bit groups and generate the square of the k-bit input value.

Abstract: A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e.g.

Abstract: An improved programmable logic device includes a set of I/O cells, a set of logic blocks, and a routing pool that provides connections among the logic blocks and the I/O cells. At least one of the logic blocks includes a programmable logic array that generates product term output signals on product term output lines. A first product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The first product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. Likewise, a second product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The second product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal.

Abstract: The present invention provides an interpreter with reduced memory access and improved jump-through-register handling. In one embodiment, a method includes storing a handler for a bytecode in a cell of a predetermined size of a table, and generating an address of the handler for the bytecode using a shift and an ADD operation. In particular, the handler address is generated by adding a base address of the table and an offset into the table. In another embodiment, a method includes prefetching a target handler address for providing improved jump-through-register handling.

Abstract: A built-in back-up power device operates a high-power apparatus for a short time period to prevent the loss of data or damage to the apparatus when power from a utility power source is interrupted. The built-in back-up power device includes a battery and a charger. The charger charges the battery when power is provided from the utility power source. During a power interruption or outage, the battery outputs back-up power to the high-power apparatus. A computer with such a built-in back-up power device is also provided.

Abstract: A method for determining the temperature of a wafer during processing is disclosed. A test wafer is specially prepared in conjunction with a calibration chart. The difference in stack sheet resistance of the test wafer before and after processing is plotted onto the calibration chart to determine the temperature of the test wafer during processing.

Abstract: A display controller in a graphics display system executes a primitive for displaying video images including multiple overlays. The primitive improves latency tolerance of the display controller and ensures seamless transitions between each frame of video images. The primitive of the present invention is executed on a display controller including a display processor. The primitive enables the display processor to process multiple control threads independently of each other. The threads execute a program to generate display signals for a frame of video image. Each of the threads executes a switch instruction when it completes processing of pixel data. The switch instruction causes the thread to determine if it is the last thread to be processed. When a thread is not the last thread, the thread is set to an inactive state. When a thread is the last thread, the primitive reactivates the multiple control threads to process pixel data for the next frame video image.