Abstract: A method and apparatus for determining synchronization and loss of synchronization in a high speed multiplexed data system. The system also includes a plurality of justification control bits and a backwards compatibility flag that allows the system to operate with older systems that have fewer justification control bits.

Abstract: A soft-switched full-bridge pulse-width modulated (“FB PWM”) converter includes a coupled inductor provides ZVS conditions over a wide range of input voltages and output loads. Further, the FB PWM converter of the present invention requires neither a large leakage inductance in the transformer, nor an external inductor, to achieve ZVS.

Abstract: A processor system includes an on-chip, split-transaction bus with independent address/control and data buses. Arbitration and bus acquisition protocols are performed on the address/control bus. An arbiter arbitrates I/O requests and regulates concurrent ownership of the split-transaction bus by assigning a virtual channel to each bus request. Data bus access is granted to a virtual channel on a priority basis, s so as to utilize to a maximum extent the available bandwidth of the data bus. In one embodiment, the data bus is preempted by another virtual channel when current virtual channel using the data bus becomes idle due to, for example, latencies in the data stream. Rearbitration, however, is avoided when the interrupted data transfer resumes, owing to state information regarding the data transfer stored in the master and slave modules of each virtual channel.

Abstract: An in-system programmable (ISP) system can be programmed by remote access from a host programming system. The remote access can be accomplished over a wired data network, a wireless data network, a radio channel, or any combination of the above. In the ISP system, an ISP controller receives control and programming data through the access interface to program ISP devices in accordance with ISP programming conventions. The ISP controller can be provided by an integrated circuit having a microprocessor core.

Abstract: A technique, which substantially reduces the number of power-stage and control circuit components in an isolated DC/DC converter with parallel current-doubler rectifier stages, includes on the primary side transformers with serially connected primary windings each having a corresponding secondary winding coupled to one of the voltage-doubler stages. In one embodiment, the primary and secondary windings and filter inductors of the current-doubler rectifier stages are provided on an integrated magnetic core. The filter inductors in each current-doubler rectifier stage can be provided as coupled inductors. In one embodiment, an X-shaped magnetic core is provided to achieve coupled or uncoupled filter inductors.

Abstract: Identification of within-wafer and wafer-to-wafer variations in yield induced by processing steps in a multi-step manufacturing process. Methods are implemented along with wafer position tracking for process control of the manufacturing process. Wafers are systematically rotated according to their position in a batch before entering a processing step. Wafer position tracking analysis of rotated wafers advantageously reveals a static pattern on each wafer regardless of position in a batch. Alternatively, data reduction methods provide a compact representation of site-specific yield data. The data reduction methods use multidimensional scaling to determine distance factor scores and angle factor scores. The distance factor scores track changes in pattern on the wafers. Wafers similar in pattern regardless of rotation angle have similar distance factor scores. The angle factor scores track rotation of patterns on wafers.

Abstract: A dual damascene process and structure for fabricating semiconductor devices are disclosed. In one embodiment of the invention, a protection layer is deposited on top of a metal layer to protect the metal layer during subsequent etching of an oxide layer to form the via and damascene trench. Because the selectivity between the oxide layer and the protection layer is high, the number and complexity of processing steps are thereby reduced. Other embodiments of the present invention use a metal sealant layer and/or anti-reflective coating in conjunction with the protection layer in a dual-damascene process.

Abstract: A bandgap voltage reference circuit with no error amplifier circuit includes a chain of complementary emitter follower circuits that are connected to a supply voltage and to common ground via respective current mirrors. Each emitter follower circuit within the chain of emitter follower circuits generates a base to emitter voltage. Because of the successive configuration of the chain of emitter follower circuits, the base to emitter voltage differences from all the emitter follower circuits are summed together. Using a chosen number of emitter follower circuits along with an appropriately chosen area for the emitters of the transistors within the emitter follower circuits, the desired proportional to absolute temperature voltage is generated. Further, because of the additive nature of the base to emitter voltage differences, as opposed to a multiplicative nature as found in conventional circuits, the bandgap voltage reference circuit has a decreased level of noise and process sensitivity.

Abstract: A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e.g.

Abstract: A shallow abrupt junction is formed in a single crystal substrate, for example, to form a pn junction in a diode or a source drain extension in a transistor. An amorphous layer is formed at the surface of the substrate by implanting an electrically inactive ion, such as germanium or silicon, into the substrate. The amorphous/crystalline interface between the amorphous layer and the base crystal substrate is located at the depth of the desired junction. A dopant species, such as boron, phosphorus or arsenic is implanted into the substrate so that peak concentration of the dopant is at least partially within the amorphous layer. The amorphous layer can be formed either before or after the implanting of the dopant species. A low temperature anneal is used to recrystallize the amorphous layer through solid phase epitaxy, which also activates the dopant within the amorphous layer. The dopant located beneath the original amorphous/crystalline interface remains inactive.

Abstract: A method of manufacturing devices with source, drain and extension regions is provided. To achieve in the extensions a depth and dopant levels different from the source and drain regions, a channel-shaped oxide structure is formed surrounding a polysilicon gate. The channel-shaped oxide structures forms an implantation barrier over the extensions region. Thus, when the source and drain implantation is carried out at a given energy, the extension regions receives a 35-40 percent dopant dose, as compared to the dose received by the source region and the drain region.

Abstract: An input/output circuit in an In-system programmable (ISP) logic device allows an output signal from a boundary scan register to be provided as output during programming operations of said ISP logic device. Thus, the ISP logic circuit can provide valid data output to other circuits interfaced to the ISP logic circuit during programming of the ISP logic device, thereby obviating a need to reset the system after reprogramming of the ISP logic device.

Abstract: A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

Abstract: A highly efficient bit encoder and a method related thereto are provided. The bit encoder transmit DC-balanced digital signals over a transmission line. To provide a DC-balanced signal, an input word's single-word disparity (SWD) value is compared to a running word disparity (RWD) value retrieved from a memory register. The RWD value indicates the cumulative DC-imbalance on the transmission line. If the disparity relationship of the SWD and the RWD satisfy a set of predefined rules, the input word is inverted to thereby offset the RWD. An inversion bit is appended to the digital input word to provide an output digital word to indicate to a receiver whether the transmitted output word is inverted to thereby permit recovery of the original system word. In one application, the DC-balanced signal transmits alternately control words and data words.

Abstract: A pipelined instruction dispatch or grouping circuit allows instruction dispatch decisions to be made over multiple processor cycles. In one embodiment, the grouping circuit performs resource allocation and data dependency checks on an instruction group, based on a state vector which includes representation of source and destination registers of instructions within said instruction group and corresponding state vectors for instruction groups of a number of preceding processor cycles.

Abstract: The concentration of metal atoms in a field area between two trench structures is determined by applying a voltage on one of the trench structures and grounding the other. The resultant current flow between the trench structures is measured and used as an indicator of metal concentration in the field area.

Abstract: A method and apparatus provide polishing of a semiconductor wafer or other substrate. The apparatus includes multiple wafer carriers provided on the top surface of a table. A semiconductor wafer is seated face-up in the wafer carrier. Each wafer carrier is driven by an electric motor to rotate at a low speed. During operation, each wafer carrier is positioned at a work station where a specified task is performed. The table rotates when the task at each station is completed to move the wafers from station to station. Thus multiple tasks relating to polishing (e.g., buffing and drying) can be carried out in parallel. At one station, a polishing pad is positioned by a polishing pad carrier face-down to polish the surface of the semiconductor wafer. A motor drives the polishing pad to move in a high-speed circular motion.

Abstract: A laser scatterometer used, e.g., to detect defects on memory media, includes a beam block that can be finely adjusted so as to block specular light while maximizing the small angle scattered light that is received by the light detector. The beam block may be adjusted independently of the light detector or may be a masked beam block that is adjusted with the entire light detector. The light source produces a light beam that is focused so as to maximize the spot size on the object being tested while minimizing the spot size at the beam block, which advantageously maximizes the small angle scattered light while decreasing testing time. The large spot size at the object being tested permits detection of large defects. Thus, disks may be quickly tested, e.g., during the burnishing process, to determine if there are any large defects.

Abstract: An N-way Circular Phase Interpolator interpolates the N phases of a reference clock signal to generate a tunable clock. By using more than two phases for interpolation, high excess frequencies as well as high precision (i.e. small jitter) are achieved. The N-way Circular Phase Interpolator provides for analog filtering in the phase domain, which attenuates the out-of-band phase noises thus further reducing the output jitter.

Abstract: A voltage control circuit that narrows the distribution of threshold voltages of memory cells by using nonlinearly incremented programming voltages. To do so, the voltage control circuit applies to the memory cells a first program pulse of a first voltage, a second program pulse of a second voltage to the memory cell, and a third program pulse of a third voltage, where the difference between the third voltage and the second voltage is less than the difference between the second voltage and the first voltage.