Abstract: An interconnect array formed at least in part using repeated application of an interconnect pattern is described. The interconnect pattern has at least ten interconnect locations. One of the ten interconnect locations is for a power interconnect. Another one of the ten interconnect locations is for a ground interconnect. At least eight interconnect locations remaining are for additional interconnects. The at least eight remaining interconnect locations are disposed around a medial region, where either the ground interconnect or the power interconnect is located in the medial region. An offset region has one of either the ground interconnect or the power interconnect not in the medial region. The interconnect array is at least partially formed by repeated application of the interconnect pattern offset from one another responsive to the offset region.

Abstract: Apparatus for vector generation is described. A vector generator is associated with a discrete power series symmetric about at least one term and configured to provide vectors, such as QSvectors for a Turbo Code for example. The vectors are each provided in separate portions as a first portion and a second portion. The second portion of a vector of the vectors is generated from the first portion of the vector using symmetry about the at least one term.

Abstract: Simulation of noise and, more particularly, a coefficient generator for channel modeling, is described. A spectrum memory is for storing sets of constants for respective harmonics. At least one phase noise source is configured for generating phase noise. An Inverse Fourier Transform block is coupled to the spectrum memory and to the at least one phase noise source. The Inverse Fourier Transform block is configured to provide a read address to the spectrum memory for accessing at least one constant of a set of constants of the sets of constants from the spectrum memory and coupled to receive the phase noise from the at least one phase noise source.

Abstract: Method and apparatus for a dynamically reconfigurable system monitor (20) are described. A system monitor (20) has registers (206) accessible via a reconfiguration port (201). At least one of the registers may be dynamically reconfigured via the reconfiguration port (201) to select a channel to be monitored or to store an alarm value to be used in monitoring by the system monitor (20). Additionally, the system monitor (20) may be embedded in a columnar block architecture.

Abstract: Method and apparatus for indicating to a coprocessor when the coprocessor can update internal register content thereof without negative repercussion to a processor is described. A controller is coupled between the coprocessor and a processor, where the controller is configured with a state machine to track the instruction through pipeline stages of the processor.

Abstract: Method of informing a processor that a coprocessor instruction is not executable by a coprocessor is described. The coprocessor, instantiated in configurable logic, is configured to execute a subset of coprocessor instructions, excluding user-selected instructions not instantiated. The processor is coupled to the coprocessor via a controller. The coprocessor instruction is sent from the processor to the controller, which queries control logic to determine whether the coprocessor is configured to execute the coprocessor instruction. If a control bit is set to disable an instruction or group of instructions, the coprocessor instruction is not executable by the coprocessor.

Abstract: Method and apparatus for transmission of information is described. A first transceiver has transmitter reconfigurable logic and a second transceiver has receiver reconfigurable logic. The first transceiver communicates with the second transceiver via a communication channel. The transmitter reconfigurable logic is configured to transmit preamble information and to receive a measurement of the preamble information. The receiver reconfigurable logic is configured to measure the preamble information and to transmit the preamble information measured. The preamble information is communicated via the first transceiver to the second transceiver via the communication channel. The receiver reconfigurable logic of the second transceiver measures the preamble information communicated. The measurement of the preamble information is sent via the receiver reconfigurable logic of the second transceiver to the first transceiver via the communication channel.

Abstract: Method and apparatus for testing input/output circuits of an integrated circuit are described. An integrated circuit includes input/output circuits having input/output pads. The input/output pads are capable of being coupled together to a tester channel. The input/output circuits each are configurable via configuration circuitry to be in either a first mode or a second mode responsive to a select circuit of the configuration circuitry coupled to receive a first input for the first mode and a second input for the second mode. The select circuit is controlled responsive to a control select signal common to all or a portion of the select circuits of each of the input/output circuits.

Abstract: A system for providing a pre-programmed integrated circuit including programmable logic, and method for providing same. The system includes: nonvolatile memory capable of having first data stored therein and an integrated circuit coupled with the nonvolatile memory. The first data is associated with a predetermined design, and the integrated circuit includes programmable logic having a user region and a reserved region. The integrated circuit is configured to obtain the first data from the nonvolatile memory for instantiation of the predetermined design in the reserved region.

Abstract: A hard macro-to-user logic interface of an integrated circuit is described. The integrated circuit includes a core as an application specific circuit block with a transaction interface of a first bit width and includes programmable logic capable of being programmed to instantiate user logic. The user logic has a user interface of a second bit width substantially less than the first bit width. A wrapper circuit couples the user interface and the transaction interface for coupling the core to the user logic.

Abstract: Method for power estimation for mobile devices for content downloading is described. More particularly, likelihood of download success is determined responsive to user selection of downloadable content after establishment of a connection between a mobile device and a network. Capabilities of the mobile device are obtained. The power level of the mobile device is obtained. At least one download data rate is determined. A likelihood of success for downloading the downloadable content selected responsive to the at least one download data rate, the power level of the mobile device, and at least one capability from the capabilities of the mobile device is determined.

Abstract: Preventing transistor damage to an integrated circuit is described. The circuit includes a switch with a first pair of p-type transistors respectively coupled in source-drain parallel with second pair of p-type transistors for preventing Negative Bias Temperature Instability (“NBTI”) damage to the second pair of p-type transistors. The switch is configured to such that when in a state associated with causing, or potentially causing, NBTI damage, both of the second pair of p-type transistors are in an OFF state for preventing NBTI damage thereto.

Abstract: Reset of an interface device of an integrated circuit is described. A Peripheral Component Interconnect Express core is instantiated as an application specific circuit block in the integrated circuit. The core has a reset block configured to be in either a hierarchical reset mode or a hierarchical/separate reset mode. In the hierarchical reset mode, the reset block is configured to assert a reset signal selected of a plurality of reset signals and to automatically assert each and every other reset signal of the plurality of reset signals lower in a reset hierarchy than the reset signal selected.

Abstract: Method and apparatus for coding and, more particularly, for Reed-Solomon encoding and decoding with puncturing are described. At least one core is generated responsive to a puncture pattern input provided to a core generator. The core may be an encoder core or a decoder core, or a combination thereof such as a CODEC. For this generation, the puncture pattern input, including puncture patterns, are for a polynomial generator. The at least one core is configured to provide encoding or decoding, as applicable, responsive to the puncture patterns for which it was configured as generated with the core generator.

Abstract: Method and apparatus for digital frequency synthesis are described. A frequency synthesizer has an accumulator, an adder, and a predictive filter. The adder is configured to subtract a predicted error from a phase profile signal. A quantized version of the phase profile signal is separated from an error portion thereof. The predictive filter, set for a fraction of a sample frequency bandwidth, is coupled to receive the error portion for generation of a next predicted error. A storage device has digital representations of sinusoidal signals accessible responsive to the quantized version of the phase profile signal. A digital-to-analog converter is coupled to receive a digital representation of a sinusoidal signal obtained from the storage device to provide an analog sinusoidal signal. An anti-imaging filter is coupled to receive the analog sinusoidal signal and configured to filter out noise.

Abstract: Generation of a random sequence using alpha particle emissions is described. A device includes memory cells, an alpha particle emitter, and read circuitry. The memory cells are sensitive to alpha particle emissions. The alpha particle emitter is proximate to the memory cells for changing state of one or more bits of the memory cells within a period of time. The read circuitry is coupled to the memory cells and configured to periodically issue a read command to periodically read the memory cells.

Abstract: Method and apparatus for configuring a programmable logic device to perform testing on a signal channel is described. Configurable logic of the programmable logic device is configured for a test mode. Configurable interconnects are configured for communication from or to the configurable logic to or from transceivers coupled to the configurable input/output interconnect to communicate test signals.

Abstract: A controller interface between a processor and a coprocessor is described. The controller is coupled to the processor to provide a processor interface for operating at a first frequency, where the first frequency is a frequency of operation of the processor. The controller is coupled to the coprocessor to provide a coprocessor interface for operating at a second frequency, where the second frequency is a frequency of operation of the coprocessor which is slower than or equal to the first frequency. The controller is configured to operate at both the first frequency and the second frequency providing in part handshaking between the processor and the coprocessor such that the processor does not have to be slowed down to the second frequency for operation with the coprocessor.

Abstract: Method and apparatus for packet detection is described. More particularly, a signal having sub-signals is received. The signal is quantized (“re-quantized”) to provide a quantized signal to processing units, where the quantized signal is a sequence of samples. A cross-correlation is done between the sequence of samples and a reference template, including totaling partial results from the processing units to provide a result. The result is a symbol timing synchronization responsive to the cross-correlation, which is provided in part by combining by addition or subtraction a regression vector obtained from the sequence of samples and a coefficient term vector obtained from the reference template.

Abstract: Reconfiguration of a hard macro via configuration registers is described. An integrated circuit includes configuration memory cells coupled to a hard macro via configuration registers. The configuration memory cells are for storing values for initializing the hard macro. The configuration registers are coupled to be loaded with the values stored by the configuration memory cells. Write management busing is coupled to the configuration registers for overwriting at least one of the values loaded into the configuration registers for reconfiguration of the hard macro.