Abstract: A receive-side client interface for a media access controller embedded in an integrated circuit having programmable logic is described. A media access controller core includes a receive engine. A receive-side datapath is coupled to the media access controller core. The receive-side datapath configured is configured to operate at two frequencies to accommodate the programmable logic in the integrated circuit.

Abstract: Method for in-system signal analysis is described. A programmable logic device is coupled within a signal communications system. A signal processing core is instantiated in programmable logic of the programmable logic device. At least one communication signal is provided to the programmable logic device, where the at least one communication signal has a first frequency. The at least one communication signal is sampled at a second frequency which is less than the first frequency to obtain samples thereof. The samples are converted from analog signals to digital signals. The digital signals are analyzed with at least in part the signal processing core.

Abstract: Method and apparatus for testing duty cycle at an input/output node is described. A test signal is generated having a non-zero frequency and a duty cycle. The test signal is sampled using a sampling signal. The phase of the sampling signal is shifted to detect a first level change in the sampled test signal. The phase of the sampling signal is then shifted to detect a second level change in the sampled test signal. The duty cycle of the test signal is computed using a phase indicator of the sampling signal at the first level change and a phase indicator of the sampling signal at the second level change.

Abstract: A carry circuit having a power-save mode and a method for reducing power consumption of an integrated circuit are described. A power-save input is selected for control select signaling. A voltage level input is selected as an initial carry input. The initial carry input is propagated through a carry stage responsive to the carry input and the control select signaling. The carry stage is placed in a first non-switching steady state mode responsive to the propagating of the initial carry input through the carry stage.

Abstract: Method and system for dynamically adjusting performance of circuitry blocks are described. A first circuit domain is coupled to an interim storage device. The first circuit domain includes a first level shifter coupled to an input of a first circuitry block and a second level shifter coupled to an output of the first circuitry block. The second level shifter is coupled between the output of the first circuitry block and an input of the interim storage device. A controller is coupled to the first circuit domain for adjustment of a first operating voltage of the first circuit domain.

Abstract: A method and apparatus for selecting programmable interconnects to reduce clock skew is described. A routing tree for clock signals is created having routes and clock pin nodes. Delays of the clock signals to the clock pin nodes are determined. The routing tree is balanced to a target clock skew, such as zero clock skew, for the clock signals provided to the clock pin nodes. Programmable interconnect circuits are selectively added to reduce clock skews of the clock signals, where the clock skews being reduced at the clock pin nodes are for at least a portion of the clock pin nodes. Additionally described are determining clock propagation delays to clock pins and balancing a clock tree using computer aided design.

Abstract: An integrated circuit that accesses memory from data lines in multiple word increments having distributed error correction coding circuitry is described. The data lines are selectively coupled to a portion of the memory for a read of data stored in the portion of the memory. The read includes providing in parallel in the multiple word increments the data stored in the portion of the memory. The data lines are selectively tapped to provide the data from the read to flow in parallel in a first direction and in a second direction. The first direction provides the data to the data registers, and the second direction provides the data to be propagated in an error checking matrix of the distributed error correction coding circuitry.

Abstract: An integrated software tool for system noise management is described. A system noise management suite for an assembly includes an integrated circuit design to be coupled to a circuit board design. The system includes three modules and a user interface. The first module is configured to determine at least one type of bounce voltage for the assembly. The second module is configured to identify decoupling capacitances for the assembly to reduce power distribution system noise. The third module is configured to estimate jitter caused by the integrated circuit design. The user interface is coupled to the first module, the second module, and the third module for input of information for the first module, the second module, and the third module.

Abstract: Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.

Abstract: A method for address filtering is described. A host interface including device registers is provided. A user program is initiated for loading of data and control information respectively into a first data register and a control register of the device registers. Responsive to the loading, hardware is initiated for writing of information loaded into the first data register into a host interface register, where the first data register is associated with an address table configuration entry and the information includes read or write information and address information. Responsive to the read or write information and the address information, a multicast address is obtained from storage; a first portion of the multicast address is deposited into the first data register; and a second portion of the multicast address is deposited into a second data register.

Abstract: A method for determining an allowable simultaneous switching output level on a bank-by-bank basis is described. An inductance scaling factor is determined for a first bank. A noise limit scaling factor is determined for the first bank. A bounce voltage scaling factor is determined for the first bank. The inductance scaling factor, the noise limit scaling factor, and the bounce voltage scaling factor are multiplied with one another to provide the simultaneous switching output level for the first bank.

Abstract: A method for noise suppression for a system implementation of an integrated circuit design is described. First clock operating parameters for logic blocks of the integrated circuit design are obtained. Second clock operating parameters for input/output banks of the integrated circuit design are obtained. At least one switching frequency associated with at least one power supply source is obtained. First and second capacitor values for the at least one power supply source are determined responsive to the first clock operating parameters, the second clock operating parameters, and the at least one switching frequency. The first capacitor values are associated with a first frequency range of operation and the second capacitor values are associated with a second frequency range of operation which is higher than the first frequency range of operation. Third capacitor values for suppression of anti-resonances are determined.

Abstract: Method and apparatus for interpolation of signals from a delay line is described. An input signal is obtained from which progressively delayed input signals are generated from the input signal. Two of the progressively delayed input signals are accessed and interpolated to provide a phase-adjusted signal.

Abstract: Method and apparatus for generating a test program for an integrated circuit having an embedded processor. One embodiment has a system which includes an embedded microprocessor; a plurality of assembly language instructions stored in a memory, where the assembly language instructions substantially exercise a critical path or a path closest to the critical path in the embedded microprocessor; and programmable test circuitry having a programmable clock circuit for providing a multiplied clock signal to the embedded microprocessor in order to execute the assembly language instructions.

Abstract: Determining voltage level validity for a power-on reset condition is described. A supply voltage is applied to an integrated circuit. An oscillating signal is generated responsive to the supply voltage applied. A counting occurs responsive to oscillations of the oscillating signal. A triggering occurs responsive to reaching a first voltage level of the supply voltage for the power-on reset condition. A first count of the counting occurs responsive to the triggering. A second count is selected responsive to the first count. A second level is accepted as having at least met a threshold for the supply voltage responsive to the counting reaching the second count for the power-on reset condition.

Abstract: Voltage level translation for open-drain circuitry is described. A logic isolation circuit includes a first buffer circuit configured for being switched between a first voltage transferable state and a first voltage non-transferable state. A first latch circuit is configured for being switched between a first reset state and a first non-reset state, the first reset state for setting the first latch circuit to a first reset condition. A second buffer circuit and second latch circuit are configured like the first buffer circuit and the first latch circuit. First and second input/output nodes are coupled to receive first and second logic level voltages, respectively. The first logic level voltage and the second logic level voltage are both for a same logic state, but the second logic level voltage is significantly greater than the first logic level voltage.

Abstract: A method and apparatus for a CPLD-structured ASIC. Circuit blocks associated with a programmed portion of a CPLD are configured to preserve timing associated with instantiation of a circuit design in the programmed portion of the CPLD. The circuit blocks have predetermined placement information obtained from the CPLD, and the placement information is used to locate CPLD-structured ASIC cells associated with the circuit blocks.

Abstract: A method and system for concurrent data processing, and an integrated circuit having programmable logic therefor, are described. A multi-threaded application is parsed into respective threads. Data value variables, data operators, data processing order of execution, and data result variables are identified from the threads. A code listing is generated associated with each of the threads for the data value variables, the data operators, the data processing order of execution, and the data result variables identified. Source and destination address information is associated with the data value variables and the data result variables. The source and destination address information is ordered to preserve the data processing order of execution. A configuration bitstream is generated for instantiating thread-specific processors in programmable logic, the thread-specific processors associated with the threads each having at least a portion of the data operators.

Abstract: Testing an integrated circuit having programmable logic is described. Programmable logic is configured as a daisy-chain of registers (310-1 through 310-(N+1)) in a closed input/output loop to register a logic 1 and logic 0s. The logic states are circulated around the closed input/output loop. Operation of output blocks (210-1 through 210-N) is controlled responsive to a series of outputs (316-1 through 316-N) provided from a portion of the daisy-chain of registers (310-1 through 310-N) to selectively place an output block of output blocks (210-1 through 210-N) in an output mode responsive to the logic 1 output in the series of outputs while leaving the output blocks remaining in a non-output mode responsive to the logic 0s in the series of outputs. The output blocks (210-1 through 210-N) are commonly coupled at an output node (212) for coupling to a single test channel, as only one output block is in the output mode at a time.

Abstract: An extended bitstream, and generation thereof, for dynamically configuring a decoder. Content data is obtained to be encoded. Build settings are obtained for configuring the decoder. The content data is encoded with an encoder to provide encoded data. A configuration bitstream is generated for configuring programmable logic responsive to the build settings. The configuration bitstream is combined with the encoded data to provide the extended bitstream. The extended bitstream is self-contained to allow for configuring of the programmable logic to dynamically instantiate the decoder to decode the encoded data.