Abstract: Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.

Abstract: A dual clock interface for an integrated circuit is described. An integrated circuit includes interface circuitry. The interface circuitry has a hardwired logic block. The hardwired logic block has a clock divider circuit coupled to receive a user clock signal and a core clock signal for dividing the core clock signal responsive to a frequency of the user clock signal to provide a divided clock signal with edges aligned to the core clock signal. The divided clock signal has the frequency of the user clock signal and a phase relationship of the user clock signal. User-side logic is coupled to receive the divided clock signal for the controlled passing of information responsive to the divided clock signal. Core-side logic is coupled to receive the core clock signal for the controlled passing of information responsive to the core clock signal.

Abstract: Lane configuration of an interface device of an integrated circuit is described. A core is used to tile a portion of an integrated circuit with a first version of the core and a second version of the core. The core is an application specific circuit version of an interface device. The first version and the second version in combination have a sharable interface. Each of the first version and the second version has N lanes. The first version is a primary version and the second version is a secondary version responsive to a shared interface mode. The N lanes of the second version are combined with the N lanes of the first version via the sharable interface for providing 2-by-N lanes of input/output to the first version.

Abstract: A method for scheduling channel usage for an over-the-air (“wireless”) network downlink is described. Information associated with incoming traffic and outgoing traffic to a node as associated with user equipment is obtained. The user equipment is capable of establishing a communication link with the node. The information obtained is placed in respective queues, which are each associated with the user equipment. A count level of the queues is obtained. An interval rate for the incoming traffic is determined. A receive rate for the user equipment is obtained. An incoming average rate for the incoming traffic is determined. An outgoing average rate for the outgoing traffic is determined. A proportion value is generated responsive to the incoming average rate, the outgoing average rate, the receive rate, and the interval rate.

Abstract: Apparatus and method for outputting data from an integrated circuit having programmable logic for Single-Event Upset tolerant operation is described. Configuration memory associated with the programmable logic is read. Bits of the configuration memory read are error checked. Buffers are cycled to select one to load and another one to unload responsive to completion of each error checking cycle of the bits. For a cycle of the error checking, a first data portion is loaded into one buffer of the buffers for the cycle, it is verified whether the bits are valid for the cycle, and a second data portion is unloaded from another buffer of the buffers responsive to the bits being valid for the cycle.

Abstract: Phase-to-sinusoid conversion and method for direct digital synthesis are described. At least one quadrant of values for a sinusoidal signal are real-to-finite bit resolution mapped to provide preconditioned values which are on average shifted down by half of a LSB position. The at least one quadrant of preconditioned values are stored in a lookup table. MSBs of a phase-accumulated signal are used as an address for accessing from the lookup table a sinusoid value. At least a logic 1 is added as an LSB to an interim output associated with the sinusoid value to provide an adjusted sinusoid value having a bit width greater than that of the sinusoid value to provide a digitally synthesized sinusoidal value.

Abstract: Method and apparatus for encoding configuration data is described. An integrated circuit device having a configuration interface is coupled to boot memory coupled at the configuration interface. The boot memory contains boot cores for configuring the integrated circuit device via the configuration interface. The boot cores include a configuration encoder core and an internal processor interface core. The boot cores may further include a processor core. The configuration encoder core provides a peripheral interface internal to the integrated circuit device, and the boot memory contains at least one set of instructions for encoding configuration data read from configuration memory. The encoded configuration data may be sent via the peripheral interface. Alternatively, configuration encoder core may include a configuration bitstream for instantiating an encoder in configurable resources for encoding readback configuration data.

Abstract: Enhancing relocatability of partial configuration bitstreams from a first area to a second area of programmable logic of an integrated circuit is described. A first set and a second set of logic resources of the programmable logic are identified. The first set and the second set of logic resources are respectively associated with the first area and the second area, the second area being wholly or partially offset from the first area. Differences between the first set of logic resources and the second set of logic resources are identified. The differences are associated with one or more of different types of circuit resources in each of the first area and the second area. Prohibit constraints associated with the differences are set.

Abstract: Arbitration for a processor block core is described. Master devices are associated with a processor block core embedded in a host integrated circuit (“IC”). The master devices are coupled to core logic of the host IC via a crossbar switch and a bridge, which are part of the processor block core. The crossbar switch includes an arbiter. An arbitration protocol is selected from among a plurality of arbitration protocols for use by the arbiter. Pending transactions having are polled for access to the bridge for arbitration using the arbitration protocol selected.

Abstract: Method and apparatus for dynamically connecting modules within a programmable device is described. In an example, a programmable device is programmed with modular circuits. A bitstream is obtained from a database. The bitstream includes a first portion associated with a module and a second portion associated with an interface to the module. The bitstream is then modified with configuration data to connect the interface to one or more of the modular circuits. The programmable device is then configured using the modified bitstream.

Abstract: A voltage regulator and method of voltage regulation for a power-on reset condition are described. Voltage regulation control signals responsive to the power-on reset condition are obtained. The control signals are generated with a first voltage to be associated with a second voltage to provide a first power-on-reset signal and a second power-on-reset signal which are opposite in state to one another. A portion of driver logic is tri-stated responsive to the control signals, and the second power-on-reset signal to at least impede supply to supply current leakage. Voltage is pulled up on a first output port and a second output port of the driver logic responsive to the first power-on-reset signal. A portion of a semiconductor substrate is electrically coupled to a higher one of a first voltage and a second voltage responsive to the pulling up to at least further impede the supply to supply current leakage.

Abstract: A test circuit in an integrated circuit and method of testing therewith are described. A test pattern generator provides a test pattern. A reference circuit includes a first sequential circuit coupled in series with a second sequential circuit. A circuit under test is coupled between a source sequential circuit and a destination sequential circuit to form a series. The source sequential circuit and the first sequential circuit are coupled to the test pattern generator to receive the test pattern. A comparison circuit is coupled to receive a first output from the destination sequential circuit and a second output from the second sequential circuit. The comparison circuit is configured to compare the first output with the second output to provide a signature output.

Abstract: A signal processing network and method for generating code for such a signal processing network are described. Pipeline blocks are each coupled to receive control signaling and associated information signaling from a scheduler. Each of the pipeline blocks respectively includes an allocation unit, a pipeline, and section controllers. The allocation unit is configured to provide a lock signal and sequence information to the section controllers in each of the pipeline blocks. The section controllers are configured to maintain in order inter-pipeline execution of the sequence responsive to the sequence information and the lock signal.

Abstract: In-system signal monitoring using an integrated circuit such as a programmable logic device is described. An analog-to-digital converter is disposed in the programmable logic device. A sampling bridge is coupled to provide an analog input to the analog-to-digital converter and to receive first signaling of a first frequency. A signal generator is configured to provide second signaling at a second frequency which is a fraction of the first frequency. Sample window circuitry is coupled to receive the second signaling and configured to provide third signaling to the sampling bridge at least partially responsive to the second signaling and at least partially responsive to an adjustable impedance setting of the sample window circuitry. The sample window circuitry is configured to provide an adjustable sample window within a pulse-width range.

Abstract: A method for instantiating a design in programmable logic of an integrated circuit is described. First configuration information is generated for configuration of the static portion of the design. The first configuration information includes routing information for routing static routes of the static portion of the design using interconnect lines. Second configuration information is generated for configuration of the at least one dynamic portion of the design. The first configuration information and the second configuration information are merged to provide third configuration information, the third configuration information being for configuration of the at least one module in the programmable logic.

Abstract: Method and apparatus for peak-to-amplitude ratio reduction are described. A data carrying signal waveform with sub-carrier signals (S1-1 through S1-M) is obtained. An initial peak reduction waveform (S2(m)) is obtained by selection of a portion of the sub-carrier signals (S1-1 through S1-M) for non-data carrying. The initial peak reduction waveform (S2(m)) is refined by at least one recursive iteration which combines the initial peak reduction waveform (S2(m)) with a circularly time-shifted version thereof to obtain a resultant peak reduction waveform having a peak side lobe amplitude less than that of the initial peak reduction waveform (S2(m)).

Abstract: A configurable interface for an integrated circuit is described. The integrated circuit includes a first core, where the first core is an application specific circuit version of a Peripheral Component Interconnect Express (“PCIe”) interface device. First configuration memory cells are associated with the first core, and the first configuration memory cells are for configuring the first core. The first configuration memory cells are programmable responsive to a first portion of a configuration bitstream, and the configuration bitstream is capable of including user-logic information for programming programmable logic of the integrated circuit.

Abstract: Apparatus and method for a microcontroller are described. The microcontroller includes a microprocessor having storage and bussing for accessing the storage. A portion of the bussing is coupled to hardwired operation codes, and a portion of the storage is for storing code. The hardwired operation codes are in part for placing the microprocessor into an exception handling mode. The exception handling mode includes reactivating the storage for execution of the code without having to reload the code therein.

Abstract: Signal distribution of a regional signal is described. An integrated circuit includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.

Abstract: A separate program power input is provided to a programmable logic array's memory to permit it to be programmed independently of printed circuit board power. Means are provided to isolate the program power input from the array's programmable logic circuit. Means are further provided to isolate the memory from the programmable logic circuit. The program power is not connected directly or indirectly to the programmable logic circuit thereby permitting the use of low-power devices to program the memory without connecting the printed circuit board to a power supply.