Abstract: A programmable logic device (PLD) with a JTAG port, such as an FPGA, is provided with a wireless JTAG adapter to enable wireless communications. Multiple PLDs connected with wireless-to-JTAG adapters can be wirelessly linked in a network to form a large boundary-scan chain serial interface. To communicate with the PLDs having a wireless JTAG port, a host PC running application software is also equipped with a wireless transceiver.

Abstract: Apparatus and method for an address lookup table is described. The address lookup table for a packet includes: an Internet Protocol field, a router port field, a router port interface field, and a Media Access Control (MAC) address field. Where the Internet Protocol field, the router port field, the router port interface field and the MAC address field have a total bit length less than or equal to sixty-four bits.

Abstract: Method and apparatus for timing modeling is described. More particularly, wire information, including wire lengths, is obtained from a routing output. Signals associated with such wire information are classified as input or output signals from an embedded core. Respective templates are automatically selected for the input signals and the output signals, respectively, at least in partial response to the wire lengths. Furthermore, timing information for the embedded core is obtained and classified according to condition, and the input signals and the output signals from the embedded core are determined to obtain rise and fall timing information for such signals.

Abstract: Method and apparatus for address filtering for a media access controller is described. An application specific integrated circuit block located in a programmable logic device includes a media access controller. The media access controller includes an address filter, which includes: address filter modules, a first logic tree coupled to each of the address filter modules and configured to provide a frame drop signal for delineation between a dropped frame and an address filtered frame; and a second logic tree coupled to each of the address filter modules to provide an address valid signal.

Abstract: A method for determining propagation delay differences for conductive lines of an integrated circuit is described. A first path is formed by coupling a first portion of conductive lines together. The first portion is associated with a first region of the integrated circuit. The first path is coupled in a ring oscillator, and a first delay is determined. A second path is formed by coupling a second portion of the conductive lines together. The second portion is the first portion except for at least a first conductive line in the first portion of the conductive lines being swapped for a second conductive line. The second conductive line is associated with a second region of the integrated circuit. The second path is coupled in the ring oscillator circuit. A second delay is determined, and an incremental difference between the first delay and the second delay may be determined.

Abstract: Cross-correlation of delay line characteristics is described. An integrated circuit for cross-correlation testing includes: a first ring oscillator and a second ring oscillator. The first ring oscillator includes a first test circuit, and the second ring oscillator includes a second test circuit. The first test circuit is coupled via first programmable interconnects to first ring oscillator circuitry, and the second test circuit is coupled via second programmable interconnects to second ring oscillator circuitry. The first test circuit includes a first programmable delay line, and the second test circuit includes a second programmable delay line. The first test circuit and the second test circuit are configured to provide separately controllable outputs for cross-correlation as between the first programmable delay line and the second programmable delay line.

Abstract: Address map generation is described. More particularly, static addresses are obtained. A system design at least a portion of which is for instantiation in configurable logic of an integrated circuit is obtained. The system design includes a processor. At least one predefined circuit block in the design is identified as a peripheral connected to a processor. The at least one predefined circuit block is for instantiation in the configurable logic of the integrated circuit. Assigned to the at least one predefined circuit block is a static address range which is obtained from the static addresses. An address map for the design is generated having the at least one predefined circuit block with the static address range. Thus, for example, independent designers designing separate systems having a same set of peripherals may map to the same static address ranges independent of software system builder tool version, board, or processor used.

Abstract: A statistics interface for a media access controller is described. The media access controller core includes a receive engine configured to provide a receive statistics vector associated with receive traffic. The receive engine is configured to output the receive statistics vector within an inter-frame gap over a number of receive clock cycles, where a portion of the receive statistics vector is provided with each clock cycle of the receive clock cycles.

Abstract: Signal distribution of a regional signal is described. A programmable logic device includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.

Abstract: A separate program power input is provided to a programmable logic array's memory to permit it to be programmed independently of printed circuit board power. Means are provided to isolate the program power input from the array's programmable logic circuit. Means are further provided to isolate the memory from the programmable logic circuit. The program power is not connected directly or indirectly to the programmable logic circuit thereby permitting the use of low-power devices to program the memory without connecting the printed circuit board to a power supply.

Abstract: Method and apparatus for a decoder interface for a processor and a coprocessor is described. An input instruction register stores an input instruction from the processor. Configuration instruction registers store instructions. Comparison/pointer logic coupled to the input instruction register and the configuration instruction registers is configured to compare the input instruction from the processor with the instructions stored in the configuration registers to determine if there is a match, and configured to provide a pointer associated with a configuration instruction register of the configuration instruction registers having a instruction of the instructions matching the input instruction, where the pointer has fewer bits than the input instruction.

Abstract: Method and apparatus for automating a sales force is described. More particularly, a sales force automation program is provided having a leads module, a commissions module and a forecasting module. Record objects, generated within a module, are automatically routed for processing. Such record objects are routed from one computer to another via the Internet. A server with the sales force automation program is coupled to a sales database for providing information from and to client computers accessing the sales force automation program.

Abstract: A programmably configurable logic-based macro is described. Portions of configuration logic blocks for interconnectivity are assigned. The portions are configured as respective shift registers. Interconnects are routed between design static locations associated to provide interconnectivity between the portions. The portions assigned and routed are saved as a macro file. Inputs and outputs of the macro file are defined in a hardware description language. The hardware description language definition of the inputs and the outputs of the macro file are synthesized to provide a bitstream for programming programmably configurable logic associated with the portions. A shift register-to-shift register module interface boundary is created within an array of the programmably configurable logic.

Abstract: Method and apparatus for encoding image data is described. In an example, a memory stores bit-planes associated with the image data. Each of the bit-planes is partitioned into data units. A bit modeler communicates with the memory and produces modeled data in response to each of the data units for each of the bit-planes. An arithmetic coder communicates with the bit modeler and produces a coded data in response to each of the modeled data produced by the bit-modeler. In another example, the bit-modeler processes at least two of the bit-planes in parallel.

Abstract: An aspect of the invention is physical layer interface for a network interface including a plurality of input/output pins. The input/output pins are coupled for being multiplexed into a physical layer interface selected from among a Reduced Gigabit Media Independent Interface and a Gigabit Media Independent Interface. The input/output pins internal to a programmable logic device are for access to and from a processor block located in the programmable logic device.

Abstract: Method and apparatus for decoding configuration data is described. A programmable logic device having a configuration interface is coupled to boot memory coupled at the configuration interface. The boot memory contains boot cores for configuring the programmable logic device via the configuration interface. The boot cores include a configuration decoder core and an internal processor interface core. The boot cores may further include a processor core. The configuration decoder core provides a peripheral interface internal to the programmable logic device, and the boot memory contains at least one set of instructions for decoding encoded data and at least one library for writing decoded encoded data to configuration memory of the programmable logic device. The encoded data is obtained from data memory via the peripheral interface.

Abstract: A programmable logic device having groups of data and instruction memory blocks separated by a processor block is described. The processor block including an embedded processor and data and instruction memory controllers. The data and instruction memory blocks respectively including data and memory groupings of block random access memories.

Abstract: Crest factor reduction in a multiband transmitter is described. Component signals (xi[n]) are respectively obtained from constituent signals. The component signals (xi[n]) are respectively associated with sub-bands. A superposed signal associated with the component signals (xi[n]) is clipped to obtain a clipping noise error signal. The clipping noise error signal is applied to the component signals (xi[n]) using a least squares estimation to project clipping noise error onto the sub-bands.

Abstract: A test circuit for fabrication of transistors for Very Large Scale Integration (“VLSI”) processing and method of use thereof are described. Transistors are formed in an array. A first decoder is coupled to gates of the transistors and configured to selectively pass voltage to the gates. A second decoder is coupled to drain regions of the transistors and configured to selectively pass voltage to the drain regions of the transistors. A third decoder is coupled to source regions of the transistors and configured to selectively pass voltage to the source regions of the transistors. A fourth decoder is coupled to body regions of the transistors and configured to selectively pass voltage to the body regions of the transistors.

Abstract: Method and apparatus for synchronizing access to a memory shared among a plurality of processors is described. In one example, each of the plurality of processors includes a primary bus for communicating with the memory and a secondary bus. A synchronization block is coupled to the secondary bus of each of the plurality of processors. The synchronization block includes at least one semaphore for controlling access among the plurality of processors to at least one data segment stored within the memory.