Patents Represented by Attorney, Agent or Law Firm Eric Webostad
  • Authentication for information provided to an integrated circuit
    Patent number: 7535249
    Abstract: A system for authentication of information provided to an integrated circuit, a method for rights management of an integrated circuit, and a method for configuring a programmable logic device are described. A memory is coupled to a programmable logic device. The memory includes an array of memory cells and storage devices. The storage devices provide a first storage space and a second storage space. The first storage space is for storing a first identifier. The second storage space is for storing a second identifier, which is a transformation of the first identifier. The array of memory cells is for storing configuration information to configure programmable logic of the programmable logic device. The configuration information includes authentication logic information.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: May 19, 2009
    Assignee: Xilinx, Inc.
    Inventor: Steven K. Knapp
  • Component naming
    Patent number: 7536377
    Abstract: Method and apparatus for component naming is described. Parameters (305) for a target component are obtained (201). The parameters (305) are hashed (202) to provide a hash value (203). The hash value (203) is used to construct a name (205) of the target component.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: May 19, 2009
    Assignee: Xilinx, Inc.
    Inventors: Roger B. Milne, Jeffrey D. Stroomer
  • Methods and systems for implementing context adaptive binary arithmetic coding
    Patent number: 7535387
    Abstract: An entropy encoder module (350) is configured to completely perform normalization of each binary input in a single clock cycle for Context Adaptive Binary Arithmetic Coding (CABAC). Outstanding bits are separated out from other bits of a portion of a frame for Context Adaptive Binary-Arithmetic Coding (CABAC). The outstanding bits are parsed responsive to location marking, counting, and bit masking to provide insert bits. The insert bits are inserted into the encoded bitstream for output. A Context Adaptive Binary Arithmetic Coding (“CABAC”) system includes: digital information storage (301) having digital video information stored therein; and a CABAC encoder (200) coupled to the digital information storage (301) to receive a portion of the digital video information at a time.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: May 19, 2009
    Assignee: XILINX, Inc.
    Inventor: Justin G. Delva
  • Integrated circuit internal test circuit and method of testing therewith
    Patent number: 7526694
    Abstract: A test circuit in an integrated circuit and method of testing therewith are described. A test pattern generator provides a test pattern. A reference circuit includes a first sequential circuit coupled in series with a second sequential circuit. A circuit under test is coupled between a source sequential circuit and a destination sequential circuit to form a series. The source sequential circuit and the first sequential circuit are coupled to the test pattern generator to receive the test pattern. A comparison circuit is coupled to receive a first output from the destination sequential circuit and a second output from the second sequential circuit. The comparison circuit is configured to compare the first output with the second output to provide a signature output.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: April 28, 2009
    Assignee: Xilinx, Inc.
    Inventors: Prabha Jairam, Himanshu J. Verma
  • Multiple supply voltage select circuit for reduced supply voltage levels
    Patent number: 7521987
    Abstract: Multiple supply voltage select circuit for use with reduced supply voltage levels and method for using same are described. A first and second set of P-channel transistors are used for voltage pull-up at a common node using two supply voltages, respectively. A P-channel transistor from each of the sets is gated by output of a respective level shifter. Both of the level shifters are biased with a higher of the two supply voltages. First and second inputs are respectively provided to the level shifters and to gates of other P-channel transistors of each of the sets.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: April 21, 2009
    Assignee: Xilinx, Inc.
    Inventors: Edward Cullen, John G. O'Dwyer, Jinsong Huang
  • Timing analysis for programmable logic devices fabricated in different Fabs
    Patent number: 7509610
    Abstract: Timing analysis of integrated circuits fabricated in different Fabs is described. A first speed file and a second speed file for a type of integrated circuit respectively fabricated in a first Fab and a second Fab are generated, the first speed file and the second speed file having corresponding types of delays. At least a portion of the corresponding types of delays have different delay values. A circuit design using the first speed file is compiled. The circuit design is for instantiation in programmable logic of the type of integrated circuit. The method further includes checking whether the circuit design as compiled using the first speed file passes timing constraints of the circuit design using the first speed file and checking whether the circuit design as compiled using the first speed file passes the timing constraints of the circuit design using the second speed file.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: March 24, 2009
    Assignee: XILINX, Inc.
    Inventor: Bernard J. New
  • Integrated system noise management—clock jitter
    Patent number: 7509608
    Abstract: A method for estimating jitter of an integrated circuit design is described. A description of logic blocks of the integrated circuit design is obtained. A description of input/output blocks of the integrated circuit design is obtained. A first type of a first jitter induced by operation of a logic block onto one or more first clock signals external to the logic block is determined. A second type of a second jitter induced by operation of an input/output block on one or more second clock signals external to the input/output block is determined.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: March 24, 2009
    Assignee: Xilinx, Inc.
    Inventor: Anthony T. Duong
  • Charge pump and voltage regulator for body bias voltage
    Patent number: 7504877
    Abstract: An integrated circuit including a voltage generator for generating a body bias voltage is described. The voltage generator includes a charge source and a voltage regulator coupled to the charge source. Transistors are coupled to the charge source to receive the body bias voltage from the voltage generator.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: March 17, 2009
    Assignee: XILINX, Inc.
    Inventors: Martin L. Voogel, Ly Nguyen
  • Bimodal source synchronous interface
    Patent number: 7502433
    Abstract: Method and apparatus for a bimodal source synchronous interface for a receiver module is described. A first input cell with a first delay chain and a first register block is provided for receipt of a forwarded clock signal by the first delay chain. A second input cell with a second delay chain and a second register block is provided for receipt of a data signal by the second delay chain. The second input cell is configured such that output from the second delay chain is coupled to a data input of the second register block. The first input cell and the second input cell may be operated in either a first modality or a second modality. The first modality may be for interfacing to a synchronous integrated circuit interface. The second modality may be for interfacing to a synchronous network/telecommunications interface.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: March 10, 2009
    Assignee: XILINX, Inc.
    Inventors: Paul T. Sasaki, Jason R. Bergendahl
  • Interconnect array formed at least in part with repeated application of an interconnect pattern
    Patent number: 7501341
    Abstract: An interconnect array formed at least in part using repeated application of an interconnect pattern is described. The interconnect pattern has at least ten interconnect locations. One of the ten interconnect locations is for a power interconnect. Another one of the ten interconnect locations is for a ground interconnect. At least eight interconnect locations remaining are for additional interconnects. The at least eight remaining interconnect locations disposed around a medial region, where either the ground interconnect or the power interconnect is located in the medial region. An offset region having the one of either the ground interconnect or the power interconnect not in the medial region. The interconnect array is at least partially formed by repeated application of the interconnect pattern off-set from one another responsive to the offset region.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: March 10, 2009
    Assignee: Xilinx, Inc.
    Inventor: Brian Von Herzen
  • Determining timing associated with an input or output of an embedded circuit in an integrated circuit for testing
    Patent number: 7493543
    Abstract: Method and system for testing an integrated circuit and more particularly, for determining timing associated with an input or output of an embedded circuit, in an integrated circuit for testing are described. A bit is adjustably delayed with a first adjustable delay to provide a delayed bit. The delayed bit is provided to a bus, such as an input bus for example, of the embedded circuit as a second vector. A third vector is output from the embedded circuit responsive to the second vector. A fourth vector is obtained having second multiple bits. The fourth vector is compared with the third vector to determine a period of delay associated with at least approximately a maximum operating frequency of the embedded circuit.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: February 17, 2009
    Assignee: XILINX, Inc.
    Inventors: Vickie Wu, Arnold Louie
  • Network media access controller embedded in a programmable logic device—transmit-side client interface
    Patent number: 7493511
    Abstract: A transmit-side client interface for a media access controller embedded in an integrated circuit having programmable logic is described. A media access controller core includes a transmit engine. A transmit-side datapath is coupled to the media access controller core. The transmit-side datapath is configured to operate at two frequencies to accommodate the programmable logic in the integrated circuit.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: February 17, 2009
    Assignee: Xilinx, Inc.
    Inventors: Robert Yin, Hamish T. Fallside, Richard P. Burnley, Nicholas McKay, Martin B. Rhodes, Douglas M. Grant, Stuart A. Nisbet, Gareth D. Edwards
  • Power gating various number of resources based on utilization levels
    Patent number: 7490302
    Abstract: Power-gating circuit resources of an integrated circuit is described. The circuit resources are associated into sets responsive to utilization levels. The associating includes providing a first set of the sets, a first number of the circuit resources in the first set being associated with a first level of utilization. The associating also includes providing a second set of the sets, a second number of the circuit resources in the second set being associated with a second level of utilization. The first number is less than the second number responsive to the first level of utilization being greater than the second level of utilization. The circuit resources of the first set are commonly coupled to a reference voltage level via a first gating circuit. The circuit resources of the second set are commonly gated to the same or a different reference voltage level via a second gating circuit.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: February 10, 2009
    Assignee: XILINX, Inc.
    Inventors: Arifur Rahman, Sean W. Kao, Sathaki Das, Tim Tuan
  • Signal adjustment for duty cycle control
    Patent number: 7489173
    Abstract: Signal phase adjustment for duty cycle control is described. A first sample clock signal and a second sample clock signal are provided. A first phase signal and a second phase signal are generated responsive to the first sample clock signal, where the first phase signal is out of phase with respect to the second phase signal. The second sample clock signal configured to be swept in phase in relation to the first phase signal. A combined signal is generated where the combined signal has a duty cycle associated with the first phase signal and the second phase signal in combination. A first counter and a second counter are clocked responsive to the second sample clock signal to count. A first count from the first counter is divided by a second count from the second counter to obtain the duty cycle associated with the combined signal.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: February 10, 2009
    Assignee: Xilinx, Inc.
    Inventors: Himanshu J. Verma, Kwansuhk Oh
  • Network media access controller embedded in a programmable logic device—host interface
    Patent number: 7484022
    Abstract: A media access controller system embedded in a programmable logic device is described. A platform dependent bridge for communicating with a first processor, where the platform dependent bridge is associated with a platform of the first processor and where the first processor is embedded in a programmable logic device. Host interface circuitry is coupled to the platform dependent bridge and is configured to provide a processor interface, where the processor interface is for communicating with the first processor via the platform dependent bridge and where the processor interface has a platform independent bus for communication with a second processor. At least one media access controller is coupled to the host interface circuitry.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: January 27, 2009
    Assignee: Xilinx, Inc.
    Inventors: Robert Yin, Hamish T. Fallside, Richard P. Burnley, Nicholas McKay, Martin B. Rhodes, Douglas M. Grant, Stuart A. Nisbet, Gareth D. Edwards
  • Phase lock detector
    Patent number: 7480361
    Abstract: Method and apparatus for phase lock detection is described. More particularly, a phase lock detection circuit (20) includes a synchronization circuit (23) coupled to receive a reference signal (31) and configured to provide a derivative signal (32). A phase lock detector (21) is coupled to receive the reference signal (31) and the derivative signal (32) and is configured to provide a cycle lock signal (24) indicating whether a phase lock exists within a lock window (57) for a clock cycle.
    Type: Grant
    Filed: July 12, 2004
    Date of Patent: January 20, 2009
    Assignee: Xilinx, Inc.
    Inventors: Qi Zhang, Atul Ghia
  • Pull-up voltage circuit
    Patent number: 7480192
    Abstract: A pull-up voltage circuit and method for reducing power consumption therewith are described. A pull-up voltage circuit has an inverter powered by a first supply voltage. A first p-type transistor and an n-type transistor are commonly gated to receive output from a first output node of the inverter to a first input node. A source region of the n-type transistor is coupled to a ground. A drain region of each of the first p-type transistor and the n-type transistor are commonly coupled at a second output node. A second p-type transistor has a gate coupled to the second output node. A drain region of the second p-type transistor, a source region of the first p-type transistor, and an input of the inverter are all coupled to a line. A source region of the second p-type transistor is coupled to the first supply voltage.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: January 20, 2009
    Assignee: XILINX, Inc.
    Inventor: Huy Son Nguyen
  • Formation of columnar application specific circuitry using a columnar programmable logic device
    Patent number: 7478359
    Abstract: A columnar programmable logic device (PLD) design converted to a columnar application specific integrated circuit-like (ASIC-like) design is described. A user design is instantiated in a PLD having a columnar architecture associated with the columnar PLD design. The columnar architecture has adjacent columns of circuitry, and one or more of the columns of circuitry as associated with instantiation of the user design in the PLD are identified. At least a portion of one or more of the identified columns are swapped with application specific circuitry for implementing all or part of the user design for converting the columnar PLD design to the columnar ASIC-like design.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: January 13, 2009
    Assignee: Xilinx, Inc.
    Inventors: Trevor J. Bauer, Steven P. Young
  • Clock stabilization detection for hardware simulation
    Patent number: 7478030
    Abstract: Method and apparatus for clock stabilization detection for hardware simulation is described. More particularly, a lock signal is obtained, for example from a digital clock module. A least common multiple (LCM) clock signal is generated, for example from a clock module. A control signal is generated at least partially responsive to the LCM clock signal and the lock signal. The control signal may be generated from a state machine and applied to select circuitry, where the control signal is used to mask application of the output clock signal responsive to the control signal.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: January 13, 2009
    Assignee: Xilinx, Inc.
    Inventors: Jonathan B. Ballagh, Roger B. Milne, Jeffrey D. Stroomer, L. James Hwang, Nabeel Shirazi
  • Ethernet media access controller embedded in a programmable logic device—clock interface
    Patent number: 7467319
    Abstract: A clock interface for a media access controller in a programmable logic device is described. The media access controller includes a clock generator for providing a clock signal to configured configurable routing of the programmable logic device to obtain a loaded version thereof. The loaded clock signal is provided to a clock network of the media access controller and to a delay cell of the media access controller to obtain an indication of the loading by the user instantiated design.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: December 16, 2008
    Assignee: Xilinx, Inc.
    Inventors: Ting Yun Kao, Robert Yin, Richard P. Burnley, Nicholas McKay, Martin B. Rhodes