Patents Represented by Attorney Eugene A. Parsons
  • Patent number: 5930164
    Abstract: A new structure of a magnetoresistive random access memory (MRAM) is presented for a high density and fast access operations. The MRAM includes two magnetic memory cells separated by an electrically conductive layer, each cell having two magnetic layers separated by a barrier layer forming a tunneling junction. Each memory cell contains one bit information as directions of magnetic vectors which are switched by an external magnetic field and sensed by a sense current flowing in the MRAM unit. The current creates a drop voltage over the MRAM unit, which indicates four different values according to the states stored in MRAM unit.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: July 27, 1999
    Assignee: Motorola, Inc.
    Inventor: Theodore Zhu
  • Patent number: 5925980
    Abstract: An organic electroluminescent device with graded region is formed, which includes a hole transporting region formed of hole transporting organic material, an electron transporting region formed of electron transporting organic material, and a graduated region disseminated between the hole transporting region and the electron transporting region. The graduated region changes, either in steps or continuously, from hole transporting organic material adjacent the hole transporting region to electron transporting organic material adjacent the electron transporting region. Electrical contacts are formed in communication with the hole transporting region and the electron transporting region.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: July 20, 1999
    Assignee: Motorola, Inc.
    Inventors: Franky So, Song Q. Shi, Cynthia A. Gorsuch, Hsing-Chung Lee
  • Patent number: 5923308
    Abstract: An array of OEDs is arranged in rows and columns with a plurality of row buses and a plurality of column buses. Each of the OEDs has a first terminal coupled to an associated row bus and a second terminal coupled to an associated column bus. A switching circuit is connected to a shadow canceling row bus of the plurality of row buses. The switching circuit is constructed to receive a shadow canceling signal on a terminal thereof and to connect the shadow canceling row bus to a pull down potential in response to the shadow canceling signal, whereby all of the OEDs in the array, other than those associated with the shadow canceling row bus, are coupled to the pull down potential and discharged.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: July 13, 1999
    Assignee: Motorola, Inc.
    Inventors: Cheng-Ping Wei, Michael P. Norman, Matthew Kim
  • Patent number: 5920500
    Abstract: A magnetic random access memory (10) has a plurality of stacked memory cells on semiconductor substrate (11), each cell basically having a portion of magnetic material (12), a word line (13), and sense line (14). Upper sense line (22) is electrically coupled to lower sense line (12) via conductor line (23) with ohmic contacts. In order to read and store states in the memory cell, lower and upper word lines (13, 18) are activated, thereby total magnetic field is applied to portion of magnetic material (11). This stacked memory structure allows magnetic random access memory (10) to integrate more memory cells on semiconductor substrate (11).
    Type: Grant
    Filed: August 23, 1996
    Date of Patent: July 6, 1999
    Assignee: Motorola, Inc.
    Inventors: Saied N. Tehrani, Xiaodong T. Zhu, Eugene Chen, Herbert Goronkin
  • Patent number: 5917848
    Abstract: A vertical cavity surface emitting laser (VCSEL) with an integrated phase shift mask for use in an optical pickup head for high density optical storage applications and a method of fabrication. The VCSEL is capable of emitting a power output of at least 10 mW. The phase shift mask is integrated with the VCSEL to allow for a 180.degree. shift in light emitted therethrough, thereby creating a reduced focal spot size for high density data write applications. The VCSEL with integrated phase shift mask is utilized in an optical pickup head capable of high density read and write applications for both CDs and DVDs.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: June 29, 1999
    Assignee: Motorola, Inc.
    Inventors: Paul Claisse, Wenbin Jiang
  • Patent number: 5917203
    Abstract: A lateral gate, vertical drift region transistor including a drain positioned on one surface of a substrate and a doped structure having a buried region therein positioned on the other surface of the substrate. The buried region defining a drift region in the doped structure extending vertically from the substrate and further defining a doped region in communication with the drift region and adjacent the surface of the doped structure. A source positioned on the doped structure in communication with the doped region and an implant region positioned in the doped region adjacent the surface and in communication with the source and buried region. An insulating layer positioned on the doped structure with a metal gate positioned on the insulating layer so as to define an inversion region in the implant region extending laterally adjacent the control terminal and communicating with the drift region and the source.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: June 29, 1999
    Assignee: Motorola, Inc.
    Inventors: Mohit Bhatnagar, Charles E. Weitzel
  • Patent number: 5917749
    Abstract: A low switching field multi-state, multi-layer magnetic memory cell including two layers of magnetic material stacked in parallel, overlying relationship and separated by a layer of non-magnetic material so as to form a portion of a multi-layer magnetic memory cell. The two layers of magnetic material being formed so that the width is less than the length and less than a width of magnetic domain walls within the two layers of magnetic material, setting a shape anisotropy easy axis along the length thereof. At least one of the two layers of magnetic material having a magnetic anisotropy generally parallel to the width of the layers of magnetic material.
    Type: Grant
    Filed: May 23, 1997
    Date of Patent: June 29, 1999
    Assignee: Motorola, Inc.
    Inventors: Eugene Chen, Saied N. Tehrani
  • Patent number: 5917204
    Abstract: AN IGBT including a collector positioned on one surface of a substrate and a doped structure having a buried region therein positioned on the other surface of the substrate. The buried region defining a drift region in the doped structure extending vertically from the substrate and further defining a doped region in communication with the drift region and adjacent the surface of the doped structure. An emitter positioned on the doped structure in communication with the doped region. An insulating layer positioned on the doped structure with a metal gate positioned on the insulating layer so as to define a conduction channel extending laterally adjacent the control terminal and communicating with the drift region and the emitter. The substrate and buried region are the same conductivity and opposite the doped region to form a bipolar transistor therebetween.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: June 29, 1999
    Assignee: Motorola, Inc.
    Inventors: Mohit Bhatnagar, Charles E. Weitzel
  • Patent number: 5914973
    Abstract: A VCSEL for high power operation and method of fabrication including a substrate element, a heat dissipation layer disposed on the substrate element, a first mirror stack, an active region lattice matched to a surface of the first mirror stack, and a second mirror stack lattice matched to a surface of the active region. An electrical contact is coupled to a surface of the active region and an electrical contact is positioned on another surface of the active region. The VCSEL is fabricated initially as two wafer structures each including a heat dissipation layer. The two wafer structures are flip mounted and the two heat dissipation layers are fused together to form a single heat dissipation layer. The structure is then selectively etched to remove a substrate element onto which the first wafer structure was formed.
    Type: Grant
    Filed: February 10, 1997
    Date of Patent: June 22, 1999
    Assignee: Motorola, Inc.
    Inventors: Wenbin Jiang, Michael S. Lebby, Jamal Ramdani
  • Patent number: 5907792
    Abstract: A method of forming a silicon nitride layer or film on a semiconductor wafer structure includes forming a silicon nitride layer on the surface of a wafer structure using a molecular beam of high purity elemental Si and an atomic beam of high purity nitrogen. In a preferred embodiment, a III-V compound semiconductor wafer structure is heated in an ultra high vacuum system to a temperature below the decomposition temperature of said compound semiconductor wafer structure and a silicon nitride layer is formed using a molecular beam of Si provided by either thermal evaporation or electron beam evaporation, and an atomic nitrogen beam provided by either RF or microwave plasma discharge.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: May 25, 1999
    Assignee: Motorola,Inc.
    Inventors: Ravi Droopad, Jonathan K. Abrokwah, Matthias Passlack, Zhiyi Jimmy Yu
  • Patent number: 5906004
    Abstract: A textile fabric including a plurality of electrically conductive fibers characterized as providing sufficient current to induce either a wired or wireless coupling between the textile fabric and a portable electronic device. The textile fabric is intended for fabrication into a functional article of clothing or other item made of the woven textile fabric, so as to increase functionality of the article of clothing or item made thereof. The plurality of electrically conductive fibers are characterized as creating an interconnect to a portable electronic device, including integrated components, electronics, or the like, or serving as an antenna for signals received and transmitted by the portable electronic device.
    Type: Grant
    Filed: April 29, 1998
    Date of Patent: May 25, 1999
    Assignee: Motorola, Inc.
    Inventors: Michael S. Lebby, Karen E. Jachimowicz
  • Patent number: 5905750
    Abstract: A semiconductor laser package including a laser chip mounted to an uppermost surface of a leadframe, and a molded structure at least partially encapsulating the laser chip. The laser chip composed of a vertical cavity surface emitting laser and an optional photodetector. The vertical cavity surface emitting laser generating an emission along a path. The molded structure including an optical element positioned a specific distance from an emission aperture of the vertical cavity surface emitting laser. The laser chip and the optical element mounted in precise z-axis alignment from the emission aperture of the vertical cavity surface emitting laser utilizing the uppermost surface of the leadframe as a dimensional reference point.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: May 18, 1999
    Assignee: Motorola, Inc.
    Inventors: Michael S. Lebby, Wenbin Jiang, John W. Stafford
  • Patent number: 5904553
    Abstract: A method of fabricating a gate quality oxide-compound semiconductor structure includes forming an insulating Ga.sub.2 O.sub.3 layer on the surface of a compound semiconductor wafer structure by a supersonic gas jet containing gallium oxide molecules and oxygen. In a preferred embodiment, a III-V compound semiconductor wafer structure with an atomically ordered and chemically clean semiconductor surface is transferred from a semiconductor growth chamber into an insulator deposition chamber via an ultra high vacuum preparation chamber. Ga.sub.2 O.sub.3 deposition onto the surface of the wafer structure is initiated by a supersonic gas jet pulse and proceeds via optimization of pulse duration, speed of gas jet, mole fraction of gallium oxide molecules and oxygen atoms, and plasma energy.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: May 18, 1999
    Assignee: Motorola, Inc.
    Inventors: Matthias Passlack, Jonathan K. Abrokwah, Ravi Droopad, Brian Bowers
  • Patent number: 5904552
    Abstract: A method of ion implanting a substrate is disclosed, which includes providing a substrate having a surface. A sacrificial layer of semiconductor material is formed on the surface and resistlessly patterning to define masked and unmasked portions. The unmasked portions are etched away to form an implantation mask on the substrate. Ions are implanted in the substrate underlying the etched away unmasked portions and the sacrificial layer is removed.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: May 18, 1999
    Assignee: Motorola, Inc.
    Inventors: Kumar Shiralagi, Danny L. Thompson
  • Patent number: 5902690
    Abstract: A non-volatile magneto-resistive memory positioned on a semiconductor substrate is shielded from stray magnetic fields by a passivation layer partially or completely surrounding the non-volatile magneto-resistive memory. The passivation layer includes non-conductive ferrite materials, such as Mn--Zn-Ferrite, Ni--Zn-Ferrite, MnFeO, CuFeO, FeO, or NiFeO, for shielding the non-volatile magneto-resistive memory from stray magnetic fields. The non-conductive ferrite materials may also be in the form of a layer which focuses internally generated magnetic fields on the non-volatile magneto-resistive memory to reduce power requirements.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: May 11, 1999
    Assignee: Motorola, Inc.
    Inventors: Clarence J. Tracy, Eugene Chen, Mark Durlam, Theodore Zhu, Saied N. Tehrani
  • Patent number: 5903586
    Abstract: A VCSEL for emitting long wavelength light including a GaAs substrate element, a first mirror stack with mirror pairs in a GaAs/AlGaAs material system lattice matched to a GaInAsN active region with an active structure sandwiched between a first cladding region adjacent the first mirror stack, and a second cladding region. The first and second cladding regions including an InGaP/GaAs material system. The active structure includes a nitride based quantum well and either a GaAsP or a GaAs barrier layer. A second mirror stack is lattice matched to the second cladding region and has mirror pairs in a GaAs/AlGaAs material system.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: May 11, 1999
    Assignee: Motorola, Inc.
    Inventors: Jamal Ramdani, Michael S. Lebby, Paul Claisse
  • Patent number: 5902130
    Abstract: A method of thermal processing a supporting structure comprised of various compound semiconductor layers having a Gd free Ga.sub.2 O.sub.3 surface layer including coating the surface layer with a dielectric or a metallic cap layer or combinations thereof, such that the low D.sub.it Ga.sub.2 O.sub.3 -compound semiconductor structure is conserved during thermal processing, e.g. during activation of ion implants of a self aligned metal-oxide-compound semiconductor gate structure. In a preferred embodiment, the semiconductor structure has a surface of GaAs, the Gd free Ga.sub.2 O.sub.3 layer has a thickness in a range of approximately 1 nm to 20 nm, and the insulating or metallic cap layer has a thickness in a range of approximately 1 nm to 500 nm.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: May 11, 1999
    Assignee: Motorola, Inc.
    Inventors: Matthias Passlack, Jonathan K. Abrokwah, Zhiyi Jimmy Yu
  • Patent number: 5902677
    Abstract: An organic electroluminescent display device (10) includes a plurality of organic layers (16, 18, and 20) disposed between opposing electrode assemblies (12 and 14). One electrode assembly (12), the anode assembly, is fabricated of a substrate (22) and electrode (24), and a layer of a compensating material (26) disposed between electrode (24) and the overlying layers of light emitting materials (16, 18, 20). Layer (26) compensates for physical mismatches between the inorganic electrode layer (24) and the organic light emitting layers (16, 18, 20).
    Type: Grant
    Filed: October 21, 1996
    Date of Patent: May 11, 1999
    Assignee: Motorola, Inc
    Inventors: Song Shi, Franky So, Hsing Chung Lee
  • Patent number: 5898612
    Abstract: First and second layers of magnetic material are stacked in parallel, overlying relationship and separated by a first layer of non-magnetic material sandwiched therebetween to form a magnetic memory cell. A layer of oxide (e.g. NiO) is positioned on either one or both major surfaces of the magnetic memory cell. The oxide has a thickness (e.g. less than approximately 150 .ANG.) which prevents the layer of oxide from pinning the first and second layers of magnetic material and adapts the layer of oxide to the first and second layers of magnetic material so as to increase the GMR ratio of the magnetic memory cell.
    Type: Grant
    Filed: May 22, 1997
    Date of Patent: April 27, 1999
    Assignee: Motorola, Inc.
    Inventors: Eugene Chen, Jing Shi
  • Patent number: 5898722
    Abstract: Dual wavelength monolithically integrated VCSELs and a method of fabrication for emitting a short wavelength light and a long wavelength light including a first mirror stack lattice matched to the surface of a substrate. A short wavelength VCSEL is fabricated and masked during the formation of a long wavelength VCSEL. Each VCSEL further including mirror pairs in a AlAs/AlGaAs material system, an active region lattice matched to a surface of the first mirror stack, and a second mirror stack lattice matched to a surface of the active region and capable of emitting either a short wavelength light or a long wavelength light, dependent upon design parameters. Electrical contacts are coupled to the active regions of the monolithically integrated short wavelength VCSEL and the long wavelength VCSEL. The dual wavelength monolithically integrated VCSELs fabricated as a semiconductor laser chip capable of read/write applications for both CDs and DVDs.
    Type: Grant
    Filed: March 10, 1997
    Date of Patent: April 27, 1999
    Assignee: Motorola, Inc.
    Inventors: Jamal Ramdani, Michael S. Lebby, Wenbin Jiang