Abstract: An integrated circuit comprises a memory device including an isolation layer for defining an active area of a substrate, a tunnel oxide layer formed on the active area, a floating gate formed over the active area and the isolation layer, an inter-gate dielectric layer formed on the floating gate, and a control gate formed on the inter-gate dielectric layer. The integrated circuit also includes a high and low voltage transistors.

Abstract: Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a capping layer are sequentially deposited on an insulating layer over a semiconductor substrate. The first interlayer insulating layer fills spaces between the conductive patterns and has a height such that when the first interlayer insulating layer is placed on the insulating layer, the first interlayer insulating layer is lower than a top surface of the capping layer but higher than a top surface of the conductive layer. The first spacer surrounds the outer surface of the capping layer on the first interlayer insulating layer.

Abstract: In a method and apparatus of aligning liquid crystal, a first ion beam is formed. The first ion beam is transformed into a second ion beam having transformed cross-section. The second ion beam advances toward a thin film including carbon-carbon double bond. The second ion beam forms a first angle with respect to the thin film. The second ion beam is transformed into an atomic beam. The atomic beam is irradiated onto the thin film to break the carbon-carbon double bond. The carbon-carbon double bond is broken to form a polarized functional group for aligning a liquid crystal molecule.

Abstract: A class AB amplifier capable of easily controlling the amount of quiescent current and the amount of amplifier output current. The amplifier includes an input circuit that transform a voltage difference between input signals into a current; a current mirror including the (the Pull Up and Pull Down transistors of the) output circuit of the amplifier controls the quiescent current through the Pull Up and Pull Down transistors output circuit; and a control circuit in the current mirror (to which a first control voltage and a second control voltage are applied), adjusts the amount of quiescent current flowing through the output circuit in a first operating mode (by controlling a first bias current that is proportionate to the quiescent current in the current mirror), and controls the amount of the output current sourced or sinked (in response to the change in the voltages at the first and second output nodes of the input circuit) in a second operating mode.

Abstract: A semiconductor device that initializes memory cells of an activated wordline group is provided. The device includes: a control signal generation circuit, which generates first and second control signals based on an activated setting signal and an initial data value during an initial value setting operation; a first power supply circuit, which supplies power to bitlines in response to the first control signal; a second power supply circuit, which supplies power to complementary bitlines in response to the second control signal; a plurality of wordlines connected to respective memory cells; and a row decoder, which selects a group of wordlines from among the plurality of wordlines based on the setting signal and a selection address and simultaneously activates the selected group of wordlines.

Abstract: A semiconductor memory device compensates leakage current. A plurality of memory cells is disposed at intersections of word lines and bit lines. A plurality of dummy cells is connected to at least one dummy bit line. A leakage compensation circuit is connected to the at least one dummy bit line that outputs a leakage compensation current to at least one of the bit lines. A read current supply circuit outputs a read current necessary for a read operation to at least one of the bit lines in response to a first control signal. The memory device is a phase-change memory device containing phase-change material. The semiconductor memory device compensates leakage current in a read operation and supplies the leakage compensation current to a selected bit line, thereby suppressing error operation occurrence caused by leakage current.

Abstract: A semiconductor device having a delay drift compensation circuit that compensates for a delay drift caused by temperature and voltage variations in a clock tree includes a clock driver having an output port, a first circuit having an input port, a first signal path between the output port of the clock driver and the input port of the first circuit and a first delay drift compensation circuit. The first delay drift compensation circuit, which is coupled with the first signal path, reduces a delay time of the first signal path when a power supply voltage increases, and increases the delay time of the first signal path when a temperature increases.

Abstract: Provided are a phase-change memory device and method that maintains a resistance of a phase-change material in a reset state within a constant resistance range. In the method, data is provided to a first phase-change memory cell and then it is first determined whether data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are not identical, a complementary write current is provided to the first phase-change memory cell and it is second determined whether the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical, data is provided to a second phase-change memory cell.

Abstract: There are provided a semiconductor memory device and a method of precharging global input/output (I/O) lines thereof, for reducing power consumption during a precharge operation. The semiconductor memory device includes a pair of first global I/O lines; a pair of second global I/O lines; a first precharge circuit for precharging the pair of first global I/O lines in response to a first precharge enable signal; a second precharge circuit for precharging the pair of second global I/O lines in response to a second precharge enable signal; a switch for connecting the pair of first global I/O lines and the pair of second global I/O lines; a first precharge driver for enabling the first precharge enable signal during a precharge operation; and a second precharge driver for enabling the second precharge enable signal during a precharge operation.

Abstract: A system and method are provided for booting a computing device using a NAND flash memory. Boot code stored in the NAND flash memory is transferred to a RAM for execution by the CPU. Operating system program stored in the NAND flash memory is transferred to a system memory for execution therefrom by the CPU after system boot.

Abstract: A charge pump circuit of a liquid crystal display driver integrated circuit (LDI) is provided, which can reduce unnecessary current consumption when a load of an output node varies is provided, where, in a gradient mode of a display-on mode, in which an output node of the charge pump circuit has a maximum load, the current driving capability of a driver in the charge pump circuit is increased, and where, in a binary mode, in which the output node of the charge pump circuit has a smaller load than in the gradient mode, the current driving capability of the driver is lower, to prevent unnecessary current consumption caused by too large driving transfer transistors in the driver and to maintain boost efficiency at a proper level.

Abstract: A NAND flash memory device which includes a first page buffer circuit reading main data bits from the main field during a read operation, a second page buffer circuit reading redundant data bits from the redundancy field during the read operation, a first column gate circuit configured to select a part of the read main data bits and a part of the read redundant data bits in response to first column selection signals at the same time, and a second column gate circuit configured to select a part of the selected main data bits in response to second column selection signals.

Abstract: A semiconductor memory device, which has an array of memory cells connected with a plurality of bit line pairs and a plurality of word lines, to perform a read or write operation of data, having low power consumption is provided. The device includes a first power supply for supplying a first power source voltage. Also, a second power supply supplies a second power source voltage having a lower voltage level than the first power source voltage. Further, the device includes a standard ground. An elevated ground circuit provides an elevated ground voltage having a higher voltage level than that of the standard ground. A first power circuit is connected with the first power supply and the standard ground, and operates in response to the first power source voltage. A second power circuit is connected with the second power supply and the elevated ground circuit, and operates in response to the second power source voltage. Thereby, power and chip size can be reduced.

Abstract: A ferroelectric random access memory (FRAM) device and a driving method thereof are provided that reduce data loss in an operation of the FRAM device. A power supply supplies a power source to the memory device. A power detection circuit detects a voltage level of the power supply and generates a detection signal when the power source has an off state. In an internal chip enable (ICE) signal generation circuit, an ICE signal is disabled to stop operation of the memory device when the ICE signal is enabled and the detection signal is applied at a first time point, and an enabled state of the ICE signal is maintained when the detection signal is applied at a second time point, wherein the operation of the FRAM device continues by control signals generated from the ICE signal.

Abstract: Disclosed is a word line driver circuit and a driving method thereof. An input to the circuit has a ground voltage level during a non-selected operating mode and, as the output signal of a word line decoding circuit, is applied at a power source voltage level during a selected operating mode. The output of the circuit has a ground voltage level during the non-selected operating mode and applies a higher voltage than the power source voltage to a word line connected to a memory cell during the selected operating mode. Optionally, a capacitor boosts the output voltage during the selected operating mode.

Abstract: A liquid crystal display (LCD) is provided. A display region formed on an array panel has a plurality of gate lines and a plurality of data lines arranged in rows and columns, respectively. A data driving unit has a plurality of first data driving integrated circuits (ICs) and a plurality of second data driving ICs located proximal to the first data driving ICs, the plurality of first data driving ICs providing first data signals to a corresponding plurality of first data lines and the plurality of second data driving ICs providing second data signals to a corresponding plurality of second data lines. A gate driving unit has a plurality of gate driving ICs for providing scanning signals to the plurality of gate lines.

Abstract: Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

Abstract: An apparatus and method for testing a computer system by utilizing a Field Programmable Gate Array (FPGA) and programmable memory modules is provided. The apparatus includes a controller, a plurality of programmable memory modules, and an FPGA. Each programmable memory module stores configuration data of peripheral devices of the computer system in corresponding versions, respectively, which are differentiated according to functions of the computer system. Each memory module stores configuration data about a PCI host controller, a memory controller, a PLL, an interrupt controller, an arbiter, a UART, or a timer. The FPGA is programmed according to data stored in one memory module selected from among the programmable memory modules. Therefore, in the apparatus, the FPGA does not contain a bus bridge circuit, so that the FPGA has an increased programmable area and can be easily connected even with peripheral devices requiring many input and output ports.

Abstract: The present invention relates to a thin film transistor and a liquid crystal display. A gate electrode is formed to include at least one portion extending in a direction perpendicular to a gain growing direction in order to make electrical charge mobility of TFTs uniform without increasing the size of the driving circuit. A thin film transistor according to the present invention includes a semiconductor pattern a thin film of poly-crystalline silicon containing grown grains on the insulating substrate. The semiconductor pattern includes a channel region and source and drain regions opposite with respect to the channel region. A gate insulating layer covers the semiconductor pattern. On the gate insulating layer, a gate electrode including at least one portion extending in a direction crossing the growing direction of the grains and overlapping the channel region is formed.

Abstract: An IC (integrated circuit) card (or smart card) comprising a plurality of detectors for detecting abnormal operating conditions of the IC card. If an abnormal condition is detected by one of the detectors, the detector will generate a detection signal, which is then stored in a nonvolatile memory. A reset signal is then generated in response to the detection signal to reset a central processor unit. The central processor unit informs a user of a reset status and a cause thereof.